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Bulletin of the American Physical Society

Demonstrating quantum speed-up in a superconducting two-qubit processor

Andreas Dewes, Romain Lauro, Florian R. Ong, Viven Schmitt, D. Estève, Patrice Bertet, D. Vion, P. Milman

Published Feb 29, 2012• 0 citations
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Currently, superconducting qubit processors are bottlenecked by errors during two-qubit gates, readout, and idle time. All three error contributions could be reduced if we improved the speed of operations (without introducing additional leakage errors) compared to the qubit lifetime. Readout and two-qubit gates are multimode interactions and therefore are limited by the coupling strength between the modes. In this thesis, we introduce a two-mode superconducting qubit which uses one mode to facilitate strong coupling to other modes of the quantum processor and one mode to store data with high coherence. Simulations show that this architecture could enable order-of-magnitude reductions in error during readout and two-qubit gates.

•Sep 1, 2025•0 citations
We operate a superconducting quantum processor consisting of two tunable transmon qubits coupled by a swapping interaction, and equipped with non destructive single-shot readout of the two qubits. With this processor, we run the Grover search algorithm among four objects and find that the correct answer is retrieved after a single run with a success probability between 0.52 and 0.67, significantly larger than the 0.25 achieved with a classical algorithm. This constitutes a proof-of-concept for the quantum speed-up of electrical quantum processors.
We operate a superconducting quantum processor consisting of two tunable transmon qubits coupled by a swapping interaction, and equipped with nondestructive single-shot readout of the two qubits. With this processor, we run the Grover search algorithm among four objects and find that the correct answer is retrieved after a single run with a success probability between 0.520.520.52 and 0.670.670.67, which is significantly larger than the 0.250.250.25 achieved with a classical algorithm. This constitutes a proof of concept for the quantum speed-up of electrical quantum processors.
Currently, superconducting qubit processors are bottlenecked by errors during two-qubit gates, readout, and idle time. All three error contributions could be reduced if we improved the speed of operations (without introducing additional leakage errors) compared to the qubit lifetime. Readout and two-qubit gates are multimode interactions and therefore are limited by the coupling strength between the modes. In this thesis, we introduce a two-mode superconducting qubit which uses one mode to facilitate strong coupling to other modes of the quantum processor and one mode to store data with high coherence. Simulations show that this architecture could enable order-of-magnitude reductions in error during readout and two-qubit gates.