In this letter, state-of-the-art fast simplified successive-cancellation (Fast-SSC) decoding is modified to cooperate with SC flip decoding. The resulting Fast-SSC-Flip decoding aims to flip the first error of invalid codewords to improve the performance of polar codes. Compared with existing Fast-SSC-Flip decoding, our decoder has about a 0.45-dB performance gain. For most undecodable codewords under Fast-SSC decoding, the proposed Fast-SSC-Flip decoding can successfully decode them much faster than prior Fast-SSC-Flip decoding.
In this letter, state-of-the-art fast simplified successive-cancellation (Fast-SSC) decoding is modified to cooperate with SC flip decoding. The resulting Fast-SSC-Flip decoding aims to flip the first error of invalid codewords to improve the performance of polar codes. Compared with existing Fast-SSC-Flip decoding, our decoder has about a 0.45-dB performance gain. For most undecodable codewords under Fast-SSC decoding, the proposed Fast-SSC-Flip decoding can successfully decode them much faster than prior Fast-SSC-Flip decoding.
Polar Codes achieve average error correction performance at finite code lengths, when decoded using Successive Cancellation (SC) decoding. Successive Cancellation Flip (SC-Flip) based decoders provide a viable low complexity substitute of the high performing high complexity Successive Cancellation List (SCL) decoders, providing a considerable improvement in the performance. A novel approach to identify and flip multiple erroneous bits in each decoding attempt has been aimed in this paper. Moreover, a faster version of the proposed decoder is also presented, which provides better performance throughout the entire decoding range. The performance of the proposed decoders have been evaluated with respect to frame error correction rate along with average normalized complexity and then compared with some of the existing works for validating the outperformance.
SC-Flip (SCF) decoding algorithm shares the attention with the common polar code decoding approaches due to its low-complexity and improved error-correction performance. However, the inefficient criterion for locating the correct bit-flipping position in SCF decoding limits its improvements. Due to its improved bit-flipping criterion, Thresholded SCF (TSCF) decoding algorithm exhibits a superior error-correction performance and lower computational complexity than SCF decoding. However, the parameters of TSCF decoding depend on multiple channel and code parameters, and are obtained via Monte-Carlo simulations. Our main goal is to realize TSCF decoding as a practical polar decoder implementation. To this end, we first realize an approximated threshold value that is independent of the code parameters and precomputations. The proposed approximation has negligible error-correction performance degradation on the TSCF decoding. Then, we validate an alternative approach for forming a critical set that does not require precomputations, which also paves the way to the implementation of the Fast-TSCF decoder. Compared to the existing fast SCF implementations, the proposed Fast-TSCF decoder has 0.24 to 0.41 dB performance gain at frame error rate of 10−3, without any extra cost. Compared to the TSCF decoding, Fast-TSCF does not depend on precomputations and requires 87% fewer decoding steps. Finally, implementation results in TSMC 65nm CMOS technology show that the Fast-TSCF decoder is 20% and 82% more area-efficient than the state-of-the-art fast SCF and fast SC-List decoder architectures, respectively.
SC-Flip (SCF) decoding algorithm shares the attention with the common polar code decoding approaches due to its low-complexity and improved error-correction performance. However, the inefficient criterion for locating the correct bit-flipping position in SCF decoding limits its improvements. Due to its improved bit-flipping criterion, Thresholded SCF (TSCF) decoding algorithm exhibits a superior error-correction performance and lower computational complexity than SCF decoding. However, the parameters of TSCF decoding depend on multiple channel and code parameters, and are obtained via Monte-Carlo simulations. Our main goal is to realize TSCF decoding as a practical polar decoder implementation. To this end, we first realize an approximated threshold value that is independent of the code parameters and precomputations. The proposed approximation has negligible error-correction performance degradation on the TSCF decoding. Then, we validate an alternative approach for forming a critical set that does not require precomputations, which also paves the way to the implementation of the Fast-TSCF decoder. Compared to the existing fast SCF implementations, the proposed Fast-TSCF decoder has 0.24 to 0.41 dB performance gain at frame error rate of 10-3, without any extra cost. Compared to the TSCF decoding, Fast-TSCF does not depend on precomputations and requires 87% fewer decoding steps. Finally, implementation results in TSMC 65nm CMOS technology show that the Fast-TSCF decoder is 20% and 82% more area-efficient than the state-of-the-art fast SCF and fast SC-List decoder architectures, respectively.
This work presents a fast successive-cancellation list flip (Fast-SCLF) decoding algorithm for polar codes that addresses the high latency issue associated with the successive-cancellation list flip (SCLF) decoding algorithm. We first propose a bit-flipping strategy tailored to the state-of-the-art fast successive-cancellation list (FSCL) decoding that avoids tree-traversal in the binary tree representation of SCLF, thus reducing the latency of the decoding process. We then derive a parameterized path selection error model to accurately estimate the bit index at which the correct decoding path is eliminated from the initial FSCL decoding. The trainable parameter is optimized online based on an efficient supervised learning framework. Simulation results show that for a polar code of length 512 with 256 information bits, with similar error-correction performance and memory consumption, the proposed Fast-SCLF decoder reduces up to 73.4% of the average decoding latency of the SCLF decoder with the same list size at the frame error rate of 10−4, while incurring a maximum computational complexity overhead of 27.6%. For the same polar code of length 512 with 256 information bits and at practical signal-to-noise ratios, the proposed decoder with list size 4 reduces 89.3% and 43.7% of the average complexity and decoding latency of the FSCL decoder with list size 32 (FSCL-32), respectively, while also reducing 83.2% of the memory consumption of FSCL-32. The significant improvements of the proposed decoder come at the cost of 0.07 dB error-correction performance degradation compared with FSCL-32.
This paper presents a fast-simplified successive cancellation (SC) flipping (Fast-SSC-Flip) decoding algorithm for polar code.Firstly, by researching the probability distribution of the number of error bits in a node caused by channel noise in simplified-SC (SSC) decoder, a measurement criterion of node reliability is proposed.Under the guidance of the criterion, the most unreliable nodes are firstly located, then the unreliable bits are selected for flipping, so as to realize Fast-SSC-Flip decoding algorithm based on node reliability (NR-Fast-SSC-Flip).Secondly, we extended the proposed NR-Fast-SSC-Flip to multiple node (NR-Fast-SSC-Flipω) by considering dynamic update to measure node reliability, where ω is the order of flipnodes set.The extended algorithm can correct the error bits in multiple nodes, and get good performance at medium and high signal-to-noise (SNR) region.Simulation results show that the proposed NR-Fast-SSC-Flip decoder can obtain 0.27dB and 0.17dB gains, respectively, compared with the traditional Fast-SSC-Flip [14] and the newly proposed two-bit-flipping Fast-SSC (Fast-SSC-2Flip-E2) [18] under the same conditions.Compared with the newly proposed partitioned Fast-SSC-Flip (PA-Fast-SSC-Flip) (𝑠𝑠=4) [18], the proposed NR-Fast-SSC-Flip-ω (ω=2) decoder can obtain about 0.21dB gain, and the FER performance exceeds the cyclic-redundancy-check (CRC) aided SC-list (CRC-SCL) decoder (L=4).
The Successive Cancellation decoder cannot provide satisfactory error correcting performance for finite length polar codes. The error performance can be improved by using Successive Cancellation Flip decoders at the expense of higher complexity. In line with this, a novel decoding approach has been developed in this paper, where distributed parity bits are used to divide the codeword into multiple segments having equal probability of error occurrence, allowing early termination. The proposed Segmented Parity Successive Cancellation Flip (SP-SC Flip) Decoder achieves lower normalized complexity and average decoding latency compared to some related existing decoders, without degrading the error correcting performance. Further improvement in decoder performance is observed when code words are divided into a greater number of segments.