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IEICE Technical Report; IEICE Tech. Rep.

Development of 30-GHz Datapath for Bit-Parallel, Gate-Level-Pipelined Rapid Single-Flux-Quantum Microprocessors

Ikki Nagaoka, Yuki Hatanaka, Matsui Yuichi, Koki Ishida, Tanaka Masamitsu, Sano Kyosuke, Taro Yamashita, Takatsugu Ono, Koji Inoue, Fujimaki Akira

Published Jan 16, 2019• 0 citations
OpenAlex

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IEEE International Superconductive Electronics Conference (ISEC)•Jul 1, 2019•3 citations
We successfully demonstrated an 8-bit-wide, bit-parallel datapath composed of an arithmetic logic unit and register files for high-throughput oriented SFQ microprocessors based on a gate-level-pipeline structure. Achieving high-speed operation in the bit-parallel datapath is difficult because of feedback paths. We used concurrent-flow clocking and counter-flow clocking in combination to solve the timing problem at the feedback path in the datapath, and we optimized the number of JJs and pipeline stages in the register file for solving the timing issue. We designed the datapath with the cell library for the AIST 10 kA/cm2^22Advanced Process. The total number of pipeline stages, Josephson junctions, and circuit area of the designed datapath were 52, 18448, and 3.81 mm × 4.05 mm, respectively. We obtained a relatively wide bias margin of the designed datapath at the target clock frequency of 50 GHz, and it operated up to 64 GHz in on-chip high-speed testing.
Rapid single-flux-quantum (RSFQ) is expected to be the next generation integrated circuit technology because of its ultra-high-speed with ultra-low-power consumption. We propose datapath circuits for an 8-bit bit-parallel RSFQ microprocessor. The proposed datapath circuits process 8-bit data each clock cycle. Seven instructions are executed in the datapath, including ADD, ADDI, IN, OUT, LOADI, SRL and MOV. The datapath circuits consist of eight input ports, eight output ports, five multiplexers (MUXs), two 8-bit data registers and one 8-bit bit-parallel arithmetic logic unit (ALU). The datapath circuits contain 12 pipeline stages and 2993 JJs based on the Open Dataset of CONNECT Cell Library for AIST ADP2 without considering wiring cells. We perform digital simulation of the proposed datapath circuits. The simulation results show correct operation with the assumed frequency of 20 GHz.