An architecture of quantum CPU

Hansika Weerasena, Prabhat Mishra

Narimani, Ali, Seyed Saeed Changiz Rezaei, Arman Zaribafiyan

The advent of new special-purpose hardware such as FPGA or ASIC-based annealers and quantum processors has shown potential in solving certain families of complex combinatorial optimization problems more efficiently than conventional CPUs. We show that to address an industrial optimization problem, a hybrid architecture of CPUs and non-CPU devices is inevitable. In this paper, we propose problem decomposition as an effective method for designing a hybrid CPU--non-CPU optimization solver. We introduce the required algorithmic elements for making problem decomposition a viable approach in meeting the real-world constraints such as communication time and the potential higher cost of using non-CPU hardware. We then turn to the well-known maximum clique problem, and propose a new method of decomposition for this problem. Our method enables us to solve the maximum clique problem on very large graphs using non-CPU hardware that is considerably smaller than the size of the graph. As an example, we show that the maximum clique problem on the com-Amazon graph, with 334,863 vertices and 925,872 edges, can be solved with a single call to a device that can embed a fully connected graph of size at least 21 nodes, such as the D-Wave 2000Q. We also show that our proposed problem decomposition approach can improve the runtime of two of the best-known classical algorithms for large, sparse graphs, namely PMC and BBMCSP, by orders of magnitude. In the light of our study, we believe that new non-CPU hardware that is small in size could become competitive with CPUs if it could be either mass produced and highly parallelized, or able to provide high-quality solutions to specific, small-sized problems significantly faster than CPUs.

Murilo Schmalfuss, Renata Reiser, Mauricio Lima Pilla +1 more

This paper presents an extension of the VPE-qGM execution environment in order to support parallel execution using OpenMP. As a relevant part of a broader project represented by the simulation framework D-GM which aims to achieve quantum simulation on hybrid architectures (clusters, multicore CPUs and GPUs), this work enables the control and execution of the simulation from multicore architectures. This proposal is shown by providing relevant management simulation on multicore CPUs, which will be later combined with GPU targeted implementations. From the synergy between these implementations, this work aims to establish a general platform for hybrid simulation, exploring different architectures usually found in clusters and expanding the capabilities of the simulation environment VPE-qGM.

Brian Marinelli, Jie Hong Luo, Kyung-Hoon Lee +2 more

Mukai Hiroto, ムカイ ヒロト, Mukai Hiroto

Min Ye, Andrii Maksymov, Nicolas Delfosse

As quantum computers advance toward the regime of MegaQuOp machines executing millions of gates, a decoding system capable of real-time error correction in such a device will be crucial. Recent efforts have been focused on decoding an error-corrected memory or a small number of logical operations. Here we demonstrate an end-to-end real-time decoding stack for a universal fault-tolerant trapped-ion quantum computer architecture capable of decoding real workloads with millions of logical gates over hundreds of logical qubits. The complete pipeline, including on the fly detector error model generation, decoding of all logical qubits, logical operations, and magic-state factories, runs on a single CPU. We benchmark the decoder on practically relevant quantum applications spanning up to 408 logical qubits, and up to one million $T$ gates. Assuming a trapped-ion architecture with 1 to 5 ms cycle time, the decoding delay stretches the computation by less than $0.3\%$ at $p_{\mathrm{CNOT}}=10^{-4}$ and less than $12\%$ at $p_{\mathrm{CNOT}}=5\times 10^{-4}$ for all workloads studied. These results demonstrate real-time decoding at MegaQuOp scale on a single conventional CPU.