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IEEE Transactions on Applied Superconductivity

Asynchronous Ballistic Reversible Fluxon Logic

Michael P. Frank, Rupert Lewis, Nancy A. Missert, Matthäus A. Wolak, Michael David Henry

Published Mar 19, 2019• 14 citations
Publisher

Abstract

In a previous paper, we described a new abstract circuit model for reversible computation called asynchronous ballistic reversible computing (ABRC), in which localized information-bearing pulses propagate ballistically along signal paths between stateful abstract devices and elastically scatter off those devices serially, while updating the device state in a logically-reversible and deterministic fashion. The ABRC model has been shown to be capable of universal computation. In the research reported here, we begin exploring how the ABRC model might be realized in practice using single flux quantum solitons (fluxons) in superconducting Josephson junction (JJ) circuits. One natural family of realizations could utilize fluxon polarity to represent binary data in individual pulses propagating near-ballistically, along discrete or continuous long Josephson junctions or microstrip passive transmission lines, and utilize the flux charge (-1, 0, +1) of a JJ-containing superconducting loop with Φ0cL0to encode a ternary state variable internal to a device. A natural question then arises as to which of the definable abstract ABRC device functionalities using this data representation might be implementable using a JJ circuit that dissipates only a small fraction of the input fluxon energy. We discuss conservation rules and symmetries considered as constraints to be obeyed in these circuits, and begin the process of classifying the possible ABRC devices in this family having up to three bidirectional I/O terminals, and up to three internal states.

DOI
10.1109/tasc.2019.2904962

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In a previous paper, we described a new abstract circuit model for reversible computation called asynchronous ballistic reversible computing (ABRC), in which localized information-bearing pulses propagate ballistically along signal paths between stateful abstract devices and elastically scatter off those devices serially, while updating the device state in a logically-reversible and deterministic fashion. The ABRC model has been shown to be capable of universal computation. In the research reported here, we begin exploring how the ABRC model might be realized in practice using single flux quantum solitons (fluxons) in superconducting Josephson junction (JJ) circuits. One natural family of realizations could utilize fluxon polarity to represent binary data in individual pulses propagating near-ballistically, along discrete or continuous long Josephson junctions or microstrip passive transmission lines, and utilize the flux charge (-1, 0, +1) of a JJ-containing superconducting loop with Φ0cL0to encode a ternary state variable internal to a device. A natural question then arises as to which of the definable abstract ABRC device functionalities using this data representation might be implementable using a JJ circuit that dissipates only a small fraction of the input fluxon energy. We discuss conservation rules and symmetries considered as constraints to be obeyed in these circuits, and begin the process of classifying the possible ABRC devices in this family having up to three bidirectional I/O terminals, and up to three internal states.
In an ongoing project at Sandia National Laboratories, we are attempting to develop a novel style of superconducting digital processing, based on a new model of reversible computation called Asynchronous Ballistic Reversible Computing (ABRC). We envision an approach in which polarized flux-ons scatter elastically from near-lossless functional components, reversibly updating the local digital state of the circuit, while dissipating only a small fraction of the input fluxon energy. This approach to superconducting digital computation is sufficiently unconventional that an appropriate methodology for hand-design of such circuits is not immediately obvious. To gain insight into the design principles that are applicable in this new domain, we are creating a software tool to automatically enumerate possible topologies of reactive, undamped Josephson junction circuits, and sweep the parameter space of each circuit searching for designs exhibiting desired dynamical behaviors. But first, we identified by hand a circuit implementing the simplest possible nontrivial ABRC functional behavior with bits encoded as conserved polarized fluxons, namely, a one-bit reversible memory cell with one bidirectional I/O port. We expect the tool to be useful for designing more complex circuits.
Reversible logic gates were previously implemented in superconducting circuits as adiabatic-reversible gates, which are powered with a sufficiently slow clock. In contrast, we are studying ballistic-reversible gates, where fluxons serve to both encode the information and power the gates. No power is applied to the gate apart from the energy of the input fluxons, and the two possible flux polarities represent the bit states. Undamped long Josephson junctions (LJJs), where fluxons move at practically constant speed from inertia, form the input and output channels of the gates. LJJs are connected in the gates by circuit interfaces, which are designed to allow the ballistic scattering from input to output fluxon states, using the temporary excitation of a localized mode. The duration of the resonant scattering determines the operation time of the gate, approximately a few Josephson plasma periods. Due to the coherent conversions between fluxon and localized modes, the ballistic gates can be very efficient: In our simulations, only a few percent of the fluxon's energy are dissipated in the gate operation. Ballistic-reversible gates can be combined with other nonballistic gate circuits to extend the range of gate functionalities. Here, we describe how the cnot can be built as a structure that includes the Identity-else-Same-gives-not (IDSN) and store-and-launch (SNL) gates. The IDSN is a 2-b ballistic gate, which we describe and analyze in terms of equivalent 1-b circuits. The SNL is a clocking gate, which allows the storage of a bit and the clocked launch of a fluxon on a bit-state-dependent output path. In the cnot, the SNL gates provide the necessary routing and fluxon synchronization for the input to the IDSN gate.
An important figure of merit for practical computing systems is energy-delay efficiency, which characterizes the number of operations a given device can perform per unit energy dissipated, per unit time taken for the operation.This efficiency metric appears to be limited in existing superconducting logic styles, motivating the search for novel, potentially more efficient forms of superconducting logic.One path to improving efficiency might be if we could remove the need for external control driven by slow clocks that is present in existing adiabatic SCE logic styles such as AQFP/RQFP.The Asynchronous Ballistic Reversible Computing (ABRC) paradigm offers an alternative model for ballistic, data-driven reversible computation.In an ongoing project at Sandia, we are attempting to demonstrate how the ABRC model can be implemented using Josephson junction circuits, while minimizing the energy-delay product.In this talk, we review the progress that has been made to date in this effort.An interesting direction for future research is to design physical mechanisms that explicitly invoke quantum processes exhibiting superadiabaticity (a.k.a."shortcuts to adiabaticity") to improve energy-delay efficiency in concrete computing technologies.We briefly review what is known about the potential applicability and limits of this approach.Dissipation-delay Efficiency (DdE) Sandia National Laboratories • The key motivating Figure of Merit (FOM) in the present study.• For a single primitive transition of the digital state of a system between two distinct informational states, consider:• The energy dissipation D incurred by that transition process.Relates to costs associated with supply of energy and cooling.• The delay d, defined as the time interval from start to end of process.Relates to costs associated with achieving a given level of parallel performance.• Then define the dissipation-delay product DdP = D • d.• Note that since refers specifically to energy dissipation, not to energy invested in the signal, in reversible processes, it is not subject to the "quantum speed limit" (QSL) lower bound of -h!No fundamental lower bound to DDP is yet known!-In fact, it would be identically zero for any perfectly-known unitary time-evolution.• Of even more general interest than DdP per se is dissipation as a function of delay, D(d), considered over a range of practical (tolerable) delay values... We'd like to extend the pareto frontier of this function within the useful range.• Dissipation-delay efficiency (DdE) of a computing technology just refers to the reciprocal of DdP, r/Dd = (Dd)-i.
Today's industrial digital logic gates are reaching a technological limit and meanwhile, superconducting circuits produce fundamentally different technologies for the future of digital computing. The standard logic is irreversible and yet superconducting circuits allow digital reversible logic with a much higher energy efficiency per gate operation. Previous reversible gate circuits were “adiabatic,” meaning that they used adiabatic-clocking waveforms for their operation power. However, we are studying logic starting from a ballistic model, where ftuxons enable gates using only energy from their inertia. Our ftuxons are defined in Long Josephson Junctions (LJJs) and may travel ballistically, similar to a particle with negligible damping. Once a ftuxon's energy approaches close enough to the gate, a resonance is induced at the gate and the ftuxon loses its definite topology. Gates are comprised of the (few Josephson-penetration-depth long) ends of LJJs and a connecting circuit interface. Only after the resonance does a ftuxon get formed and yield the gate result without external power: a ftuxon for bit-state 0 or an antiftuxon for bit-state 1. Through earlier analysis of the numerically discovered phenomena we find that dynamics can be described with ftuxon- and antiftuxon-like excitations at the ends of LJJs within the gate. The bit-switching action in our gates is resonant indicating fundamentally different dynamics than the classic model of adiabatic reversible circuits. Our ballistic Reversible Fluxon Logic (RFL) gates have no added damping and calculated energy efficiencies of over 97%. Thus in our dynamical process the “bit energy” is preserved. However, irreversible logic completely dissipates this at each operation (e.g., charging energy in CMOS or SFQ energy in irreversible SFQ logic). An RFL gate can achieve a fast gate operation since its resonance is only few JJ plasma periods. We also describe the CNOT in our technology. It is enabled by a couple of vital gates: A IDSN logic gate, similar to our other ballistic gates, and a Store-aNd-Launch (SNL) timing gate to ensure proper synchronization of the bits. The latter allows bit storage followed by launching of a data ftuxon using an adiabatic pulse from a clock ftuxon with lower energy than the data ftuxon for good CNOT efficiency.
Motivation: Improving dissipation-delay efficiency in SCE s Appears limited in existing SCE logic families (as well as in CMOS) s Can we find a new SCE logic style that may give a path forward?s Approach: Reversible computing without clocking overhead?s Adiabatic SCE logic families have dissipation/op oc 1/(transition time) Typical in classical adiabatic processes: e.g.resistance, friction, viscosity s However, quantum adiabatic processes can do better than this!Exponential adiabaticity of Landau-Zener transitions in scattering procs.s Can elastic scattering of fluxons do ballistic reversible computing?Use Asynchronous Ballistic Reversible Computing model of computation s ACl/ACS-funded project at Sandia: s Review of progress to date: LJJ interconnects, RM cell, test chip s Project plan looking forwards: Continued technology development (more circuits / experimental tests) -Also investigating whether theoretical methods of superadiabaticity / shortcuts to adiabaticity (STA) might be applied in fluxon-based systems 3 4 1 Project Plan Outline (from Proposal)