IEICE Technical Report; IEICE Tech. Rep.

Timing Extraction for Logic Simulation of VLSI Adiabatic Quantum-Flux-Parametron Circuits

Naoki Takeuchi, Xu Qiuyun, Tatsuya Narama, Yuki Yamanashi, Ortlepp Thomas, Yoshikawa Nobuyuki

Published Oct 1, 2015• 6 citations

Related papers

Investigation of Multi-Phase Timing Windows for Adiabatic Quantum-Flux-Parametron Logic

A. J. Christopher, Olivia Chen, Naoki Takeuchi +2 more

Design Methodology for Very-Large-Scale-Integration of Adiabatic Quantum-Flux-Parametron Logic Superconductor Circuits

Christopher Lawrence Ayala

Ultra-Low-Power Superconducting Logic Circuits using Adiabatic Quantum Flux Parametron

Yoshikawa Nobuyuki, Dan Ozawa, Kohei Ehara +1 more

Study of a Five-input Majority Gate using Adiabatic Quantum Flux Parametron Logic

Yuichi Yamazaki, Taiki Yamae, Naoki Takeuchi +1 more

Design and Evaluation of Compact Interfaces between Adiabatic Quantum-Flux-Parametron Logic and Rapid Single-Flux-Quantum Logic

Yuichi Yamazaki, Naoki Takeuchi, Nobuyuki Yoshikawa

Design of the Interface between Adiabatic Quantum Flux Parametron Circuits and Single Flux Quantum Circuits

Yuichi Yamazaki, Taiki Yamae, Naoki Takeuchi