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A Study on Rate Estimation Scheme for Weighted Bit-Flipping Decoding of Rate Compatible LDPC Codes

Kenji Kita, Tetsuo Tsujioka

Published Apr 17, 2008• 0 citations
OpenAlex

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Rate estimation scheme for weighted bit-flipping decoding of rate compatible LDPC codes

Kenji Kita, Tetsuo Tsujioka

This paper considers a new rate estimation scheme for rate compatible LDPC (RC-LDPC) codes. We have investigated some estimation schemes for RC-LDPC codes even though there is no side information about code rates used at a transmitter. The previous schemes were based on log-likelihood ratio of sum-product decoders at a receiver. Because of too much computational complexity, simpler estimation schemes are expected to be developed. For this purpose, we focus on a simpler decoding scheme, thus weighted bit-flipping (WBF) decoding which have been much attention by many reseachers recently. In this paper, we propose a new rate estimation scheme and evaluate its performance. Simulation results show that the proposed scheme has advantages of much effectiveness and potential for estimating code rates.

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Extensive simulations show that for some low density parity-check(LDPC)codes of low row/colum weight,the modified sum of the magnitude based weighted bit flipping(MSMWBF)decoding algorithm performs extraordinarily well.However,this dose not hold when it comes to large row/colum weight finite-geometry LDPC codes,which is first theoretically analyzed.Secondly,improvement in performance is observed for large row/colum weight LDPC codes by considering an additive offset term for the parity-check-equation reliability of the above algorithm.Simulation results show that the performance of the improved scheme is better than that of the MSMWBF algorithm about 0.63 dB at bit-error rate of 10-5 over the additive white Gaussian noise channel with only a modest increase in computational complexity.

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VLSI Implementation of a High-Throughput Soft-Bit-Flipping Decoder for Geometric LDPC Codes

Junho Cho, Jonghong Kim, Wonyong Sung

VLSI-based decoding of geometric low-density parity-check (LDPC) codes using the sum-product or min-sum algorithms is known to be very difficult due to large memory requirement and high interconnection complexity caused by high variable and column degrees. In this paper, a low-complexity high-performance algorithm is introduced for decoding of such high-weight LDPC codes. The developed soft-bit-flipping (SBF) algorithm operates in a similar way to the bit-flipping (BF) algorithm but further utilizes reliability of estimates to improve error performance. A hybrid decoding scheme comprised of the BF and SBF algorithms is also proposed to shorten the decoding time. Parallel and pipelined VLSI architecture is developed to increase the throughput without consuming much chip area. The (1057, 813) and (273, 191) projective-geometry LDPC codes are used for performance evaluation, and the former is designed in VLSI.

IEEE Transactions on Circuits and Systems I Regular Papers•May 1, 2010•12 citations
This paper considers a new rate estimation scheme for rate compatible LDPC (RC-LDPC) codes. We have investigated some estimation schemes for RC-LDPC codes even though there is no side information about code rates used at a transmitter. The previous schemes were based on log-likelihood ratio of sum-product decoders at a receiver. Because of too much computational complexity, simpler estimation schemes are expected to be developed. For this purpose, we focus on a simpler decoding scheme, thus weighted bit-flipping (WBF) decoding which have been much attention by many reseachers recently. In this paper, we propose a new rate estimation scheme and evaluate its performance. Simulation results show that the proposed scheme has advantages of much effectiveness and potential for estimating code rates.
Extensive simulations show that for some low density parity-check(LDPC)codes of low row/colum weight,the modified sum of the magnitude based weighted bit flipping(MSMWBF)decoding algorithm performs extraordinarily well.However,this dose not hold when it comes to large row/colum weight finite-geometry LDPC codes,which is first theoretically analyzed.Secondly,improvement in performance is observed for large row/colum weight LDPC codes by considering an additive offset term for the parity-check-equation reliability of the above algorithm.Simulation results show that the performance of the improved scheme is better than that of the MSMWBF algorithm about 0.63 dB at bit-error rate of 10-5 over the additive white Gaussian noise channel with only a modest increase in computational complexity.
VLSI-based decoding of geometric low-density parity-check (LDPC) codes using the sum-product or min-sum algorithms is known to be very difficult due to large memory requirement and high interconnection complexity caused by high variable and column degrees. In this paper, a low-complexity high-performance algorithm is introduced for decoding of such high-weight LDPC codes. The developed soft-bit-flipping (SBF) algorithm operates in a similar way to the bit-flipping (BF) algorithm but further utilizes reliability of estimates to improve error performance. A hybrid decoding scheme comprised of the BF and SBF algorithms is also proposed to shorten the decoding time. Parallel and pipelined VLSI architecture is developed to increase the throughput without consuming much chip area. The (1057, 813) and (273, 191) projective-geometry LDPC codes are used for performance evaluation, and the former is designed in VLSI.