Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Optics Express

FPGA implementation of rate-adaptive spatially coupled LDPC codes suitable for optical communications

Xiaole Sun, Ivan B. Djordjević

Published Jan 31, 2019• 11 citations
Publisher

Abstract

In this paper, we propose a unified field-programmable gate array (FPGA) structure for a rate-adaptive forward error correction (FEC) scheme based on spatially coupled (SC) LDPC codes derived from quasi-cyclic (QC) LDPC codes. We described the unified decoder structure in detail and showed that the rate adaptation can be achieved by a controller on-the-fly. By FPGA based emulation, the results show that, with comparable complexity, the SC codes provide larger coding gain. The implemented unified structure can be employed for any template QC-LDPC code to achieve a spatially-coupling based code-rate adaptation scheme.

DOI
10.1364/oe.27.003422

Related papers

LDPC Codes Derived from Quasi-cyclic Code Design Suitable for Optical Communications

Xiaole Sun, Ivan B. Djordjević

We propose a rate-adaptive forward error correction (FEC) scheme based on spatially-coupled (SC) LDPC codes derived from quasi-cyclic (QC) LDPC codes with its field-programmable gate array (FPGA) architecture. By FPGA emulation, we show that, with comparable computational complexity, the proposed LDPC codes provide larger coding gain and smaller error floor compare to the QC-LDPC base code. As a result, due to its hardware friendly structure, they are presented to be a promising candidate for the next-generation intelligent optical communication systems such as long-haul optical transmission system.

International Conference on Transparent Optical Networks•Jul 1, 2018•3 citations

Design and FPGA verification of a quasi-cyclic LDPC code for optical communication systems

Bergero Genaro, Damián A. Morero, Ariel L. Pola +2 more

Powerful forward error correction codes such as quasi-cyclic low density parity check (QC-LDPC) are required in next-generation coherent optical communication systems [1]. This work describes the design and experimental verification of a high net coding gain (NCG), low complexity QC-LDPC code. Towards this end, we develop a field programmable gate array (FPGA) based platform specially designed for optimization and performance evaluation of LDPC codes. The proposed FPGA framework includes several features such as the capability of changing the internal resolution of the decoder algorithm or capturing error patterns for error-floor analysis. Experimental results derived from the FPGA platform show that the designed QC-LDPC code is able to achieve an NCG of 11.6 dB at a bit-error-rate (BER) of 10-15with an overhead of 25% and a codeword length of only 16K bits.

IEEE Latin-American Conference on Communications•Nov 1, 2016•1 citation

A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes

Qing Hua Lu, Jianfeng Fan, Chiu‐Wing Sham +2 more

In this paper, we propose a new class of quasi-cyclic low-density parity-check (QC-LDPC) codes, namely cyclically-coupled QC-LDPC (CC-QC-LDPC) codes, and their RAM-based decoder architecture. CC-QC-LDPC codes have a simple structure and are constructed by cyclically-coupling a number of QC-LDPC subcodes. They can achieve throughput and error performance as excellent as LDPC convolutional codes, but with much lower hardware requirements. They are therefore promising candidates for future generations of communication systems such as long-haul optical communication systems. In particular, a rate-5/6 CC-QC-LDPC decoder has been implemented onto a field-programmable gate array (FPGA) and it achieves a throughput of 3.0 Gb/s at 100 MHz clock rate with 10-iteration decoding. No error floor is observed up to an$E_{b}/N_{0}$of 3.50 dB, where all$1.14\times 10^{16}$transmitted bits have been decoded correctly.

IEEE Transactions on Circuits and Systems I Regular Papers•Jan 1, 2016•34 citations

FPGA implementation of high-performance QC-LDPC decoder for optical communications

Ding Zou, Ivan B. Djordjević

Forward error correction is as one of the key technologies enabling the next-generation high-speed fiber optical communications. Quasi-cyclic (QC) low-density parity-check (LDPC) codes have been considered as one of the promising candidates due to their large coding gain performance and low implementation complexity. In this paper, we present our designed QC-LDPC code with girth 10 and 25% overhead based on pairwise balanced design. By FPGAbased emulation, we demonstrate that the 5-bit soft-decision LDPC decoder can achieve 11.8dB net coding gain with no error floor at BER of 10-15 avoiding using any outer code or post-processing method. We believe that the proposed single QC-LDPC code is a promising solution for 400Gb/s optical communication systems and beyond.

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE•Feb 7, 2015•6 citations

Spatially coupled codes and optical fiber communications: An ideal match?

Laurent Schmalen, Detlef Suikat, Detlef Rösener +3 more

In this paper, we highlight the class of spatially coupled codes and discuss their applicability to long-haul and submarine optical communication systems. We first demonstrate how to optimize irregular spatially coupled LDPC codes for their use in optical communications with limited decoding hardware complexity and then present simulation results with an FPGA-based decoder where we show that very low error rates can be achieved and that conventional block-based LDPC codes can be outperformed. In the second part of the paper, we focus on the combination of spatially coupled LDPC codes with different demodulators and detectors, important for future systems with adaptive modulation and for varying channel characteristics. We demonstrate that SC codes can be employed as universal, channel-agnostic coding schemes.

arXiv:1505.05405•IEEE International Workshop on Signal Processing Advances in Wireless Communications (SPAWC)•Jun 1, 2015•14 citations

A layered QC-LDPC decoder architecture for high speed communication system

Chiu‐Wing Sham, Xu Chen, Wai M. Tam +2 more

The performance of a high-throughput long-distance communication system such as an optical transmission system is limited by the Net Coding Gain (NCG) of the Forward Error Correction (FEC) system. Summarizing the previous research works, Low-Density Parity-Check (LDPC) codes form one of the most promising FEC schemes to be applied in high-throughput communication systems. Designing a practical channel coding scheme with high code rate, low complexity, high throughput and extremely low error floor has always been a very challenging problem. Quasi-cyclic low-density parity-check (QC-LDPC) codes have been promising candidates to fulfill the above requirements but the implementation issues remain. In this paper, we propose a layered QC-LDPC decoder architecture with high code rate, low complexity, high throughput and excellent error performance. The architecture has been implemented using FPGA and the error performance has been shown to be good.

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)•Dec 1, 2012•35 citations
In this paper, we propose a unified field-programmable gate array (FPGA) structure for a rate-adaptive forward error correction (FEC) scheme based on spatially coupled (SC) LDPC codes derived from quasi-cyclic (QC) LDPC codes. We described the unified decoder structure in detail and showed that the rate adaptation can be achieved by a controller on-the-fly. By FPGA based emulation, the results show that, with comparable complexity, the SC codes provide larger coding gain. The implemented unified structure can be employed for any template QC-LDPC code to achieve a spatially-coupling based code-rate adaptation scheme.
We propose a rate-adaptive forward error correction (FEC) scheme based on spatially-coupled (SC) LDPC codes derived from quasi-cyclic (QC) LDPC codes with its field-programmable gate array (FPGA) architecture. By FPGA emulation, we show that, with comparable computational complexity, the proposed LDPC codes provide larger coding gain and smaller error floor compare to the QC-LDPC base code. As a result, due to its hardware friendly structure, they are presented to be a promising candidate for the next-generation intelligent optical communication systems such as long-haul optical transmission system.
Powerful forward error correction codes such as quasi-cyclic low density parity check (QC-LDPC) are required in next-generation coherent optical communication systems [1]. This work describes the design and experimental verification of a high net coding gain (NCG), low complexity QC-LDPC code. Towards this end, we develop a field programmable gate array (FPGA) based platform specially designed for optimization and performance evaluation of LDPC codes. The proposed FPGA framework includes several features such as the capability of changing the internal resolution of the decoder algorithm or capturing error patterns for error-floor analysis. Experimental results derived from the FPGA platform show that the designed QC-LDPC code is able to achieve an NCG of 11.6 dB at a bit-error-rate (BER) of 10-15with an overhead of 25% and a codeword length of only 16K bits.
In this paper, we propose a new class of quasi-cyclic low-density parity-check (QC-LDPC) codes, namely cyclically-coupled QC-LDPC (CC-QC-LDPC) codes, and their RAM-based decoder architecture. CC-QC-LDPC codes have a simple structure and are constructed by cyclically-coupling a number of QC-LDPC subcodes. They can achieve throughput and error performance as excellent as LDPC convolutional codes, but with much lower hardware requirements. They are therefore promising candidates for future generations of communication systems such as long-haul optical communication systems. In particular, a rate-5/6 CC-QC-LDPC decoder has been implemented onto a field-programmable gate array (FPGA) and it achieves a throughput of 3.0 Gb/s at 100 MHz clock rate with 10-iteration decoding. No error floor is observed up to anEb/N0E_{b}/N_{0}Eb​/N0​of 3.50 dB, where all1.14×10161.14\times 10^{16}1.14×1016transmitted bits have been decoded correctly.
Forward error correction is as one of the key technologies enabling the next-generation high-speed fiber optical communications. Quasi-cyclic (QC) low-density parity-check (LDPC) codes have been considered as one of the promising candidates due to their large coding gain performance and low implementation complexity. In this paper, we present our designed QC-LDPC code with girth 10 and 25% overhead based on pairwise balanced design. By FPGAbased emulation, we demonstrate that the 5-bit soft-decision LDPC decoder can achieve 11.8dB net coding gain with no error floor at BER of 10-15 avoiding using any outer code or post-processing method. We believe that the proposed single QC-LDPC code is a promising solution for 400Gb/s optical communication systems and beyond.
In this paper, we highlight the class of spatially coupled codes and discuss their applicability to long-haul and submarine optical communication systems. We first demonstrate how to optimize irregular spatially coupled LDPC codes for their use in optical communications with limited decoding hardware complexity and then present simulation results with an FPGA-based decoder where we show that very low error rates can be achieved and that conventional block-based LDPC codes can be outperformed. In the second part of the paper, we focus on the combination of spatially coupled LDPC codes with different demodulators and detectors, important for future systems with adaptive modulation and for varying channel characteristics. We demonstrate that SC codes can be employed as universal, channel-agnostic coding schemes.
The performance of a high-throughput long-distance communication system such as an optical transmission system is limited by the Net Coding Gain (NCG) of the Forward Error Correction (FEC) system. Summarizing the previous research works, Low-Density Parity-Check (LDPC) codes form one of the most promising FEC schemes to be applied in high-throughput communication systems. Designing a practical channel coding scheme with high code rate, low complexity, high throughput and extremely low error floor has always been a very challenging problem. Quasi-cyclic low-density parity-check (QC-LDPC) codes have been promising candidates to fulfill the above requirements but the implementation issues remain. In this paper, we propose a layered QC-LDPC decoder architecture with high code rate, low complexity, high throughput and excellent error performance. The architecture has been implemented using FPGA and the error performance has been shown to be good.