A quantum computer fundamentally comprises a quantum processor and a classical controller. The classical electronic controller is used to correct and manipulate the qubits, the core components of a quantum processor. To enable quantum computers scalable to millions of qubits, as required in practical applications, the simultaneous optimization of both the classical electronic and quantum systems is needed. In this paper, a co-design methodology is proposed for obtaining an optimized qubit performance while considering practical trade-offs in the control circuits, such as power consumption, complexity, and cost. The SPINE (SPIN Emulator) toolset is introduced for the co-design and co-optimization of electronic/quantum systems. It comprises a circuit simulator enhanced with a Verilog-A model emulating the quantum behavior of single-electron spin qubits. Design examples show the effectiveness of the proposed methodology in the optimization, design and verification of a whole electronic/quantum system.
A quantum computer fundamentally comprises a quantum processor and a classical controller. The classical electronic controller is used to correct and manipulate the qubits, the core components of a quantum processor. To enable quantum computers scalable to millions of qubits, as required in practical applications, the simultaneous optimization of both the classical electronic and quantum systems is needed. In this paper, a co-design methodology is proposed for obtaining an optimized qubit performance while considering practical trade-offs in the control circuits, such as power consumption, complexity, and cost. The SPINE (SPIN Emulator) toolset is introduced for the co-design and co-optimization of electronic/quantum systems. It comprises a circuit simulator enhanced with a Verilog-A model emulating the quantum behavior of single-electron spin qubits. Design examples show the effectiveness of the proposed methodology in the optimization, design and verification of a whole electronic/quantum system.
A quantum computer comprises a quantum processor and the associated control electronics used to manipulate the qubits at the core of a quantum processor. CMOS circuits placed close to the quantum bits and operating at cryogenic temperatures offer the best solution for the control of millions of qubits. The performance requirements of the electronics are very stringent and its design requires the simultaneous optimization of both the circuits and the quantum system. This paper presents the SPINE (SPIN Emulator) toolset for the co-design and co-optimization of electronic/quantum systems. It comprises a SPICE simulator enhanced with a Verilog-A model based on a Hamiltonian solver emulating the quantum behavior of single-electron spin qubits. A co-design methodology is proposed to derive on the one hand the specifications of the electrical signals to be applied to and captured from the qubits, and to ensure on the other hand, the compliance of the electronics in generating the required signals. This methodology results in an optimized qubit performance while considering practical trade-offs in the control circuits, such as power consumption, complexity and cost as proven by a practical design example.
Quantum computers based on superconducting qubits have emerged as a leading candidate for a scalable quantum processor architecture. The core of a quantum processor consists of quantum devices that are manipulated using classical electronic circuits, which need to be co-designed for optimal performance and operation. As the principles governing the behavior of the classical circuits and the quantum devices are different, this presents a unique challenge in terms of the simulation, design and optimization of the joint system. A methodology is presented to transform the behavior of small-scale quantum processors to equivalent circuit models that are usable with classical circuits in a generic electrical simulator, enabling the detailed analysis of the impact of many important non-idealities. The methodology has specifically been employed to derive a circuit model of a superconducting qubit interacting with the quantized electromagnetic field of a superconducting resonator. Based on this technique, a comprehensive analysis of the qubit operation is performed, including the coherent control and readout of the qubit using electrical signals. Furthermore, the effect of several non-idealities in the system such as qubit relaxation, decoherence and leakage out of the computational subspace are captured, in contrast to previous works. As the presented method enables the co-simulation of the control electronics with the quantum system, it facilitates the design and optimization of near-term superconducting quantum processors.
Quantum computers have gained widespread interest as they can potentially solve problems that are intractable even for today’s supercomputers, such as the simulation of quantum systems as initially proposed by Feynman. To achieve such tremendous progress, a quantum computer relies on processing the information stored in quantum bits (qubits), the fundamental units of quantum computation, similar to the bits in a classical (i.e., non-quantum) processor. In general, a quantum processor comprising several qubits is connected through a quantum-to-classical interface consisting of classical electrical circuits for manipulating and reading out their quantum state. The accuracy of an operation on a qubit is characterized using the fidelity, which is 100 % in case of a perfect operation. In practice, a fidelity between 99 % and 99.9 % is typically achieved in today’s experiments with less than 100 qubits, limited by non-idealities in the control signals and by the implementation of the physical qubit itself. Since such qubit fidelities are too low to execute relevant quantum algorithms, quantum error correction schemes have been developed which rely on a much larger number of qubits to correct for possible errors, resulting in the need for quantum processors with thousands or millions of qubits. Solid-state qubits promise the largescale integration required to scale to millions of qubits, as they exploit the lithographic fabrication techniques borrowed from the semiconductor industry. However, state-of-theart solid-state qubits, such as transmons and single-electron spin qubits, must be typically cooled to cryogenic temperatures in a dilution refrigerator to exhibit quantum behavior. Because of the limited number of qubits (< 100) in state-of-theart solid-state quantum processors, the classical controller is currently implemented by general-purpose instruments or by tailor-made controllers operating at room temperature connected via several wires to the qubits in the cryogenic chamber. However, these systems must scale to support millions of qubits. While scaling up the underlying quantum processor is already exceptionally challenging, building the electronics required to interface such a large-scale processor is just as relevant and arduous.
As the number of qubits in quantum computing increases, the scalability of existing qubit circuit structures and control systems may become insufficient for large-scale expansion and high-fidelity control. To address this challenge, we propose a behavioral-level model of a superconducting qubit and its control electronics, followed by a co-simulation to evaluate their performance. In this paper, we present the modeling process, simulation procedure, and resulting design specifications for the qubit control system. Our co-simulation approach utilizes MATLAB and Simulink, enabling us to derive critical circuit design specifications, such as the required Digital-to-Analog Converter (DAC) resolution, which should be 8 bits or higher, to achieve high-fidelity control. By taking into account factors such as DAC sampling rates, integral and differential nonlinearities, and filter characteristics, we optimize the control system for efficient and accurate qubit manipulation. Our model and simulation approach offer a promising solution to the scalability challenges in quantum computing, providing valuable insights for the design of large-scale superconducting quantum computing systems.
Quantum computers1 could revolutionize computing in a profound way due to the massive speedup they promise. A quantum computer comprises a cryogenic quantum processor and a classical electronic controller. When scaling up the cryogenic quantum processor to at least a few thousands, and possibly millions, of qubits required for any practical quantum algorithm, cryogenic CMOS (cryo-CMOS) electronics is required to allow feasible and compact interconnections between the controller and the quantum processor. Cryo-CMOS leverages the CMOS fabrication infrastructure while exploiting the continuous improvement of performance and miniaturization guaranteed by Moore's law, in order to enable the fabrication of a cost-effective practical quantum computer. However, designing cryo-CMOS integrated circuits requires a new set of CMOS device models, their embedding in design and verification tools, and the possibility to co-simulate the cryo-CMOS/quantum-processor architecture for full-system optimization. In this paper, we address these challenges by focusing on their impact on the design of complex cryo-CMOS systems.
A quantum computer comprises both qubits and their classical electronic interface. While much research is currently devoted solely to qubits, an efficient electronic controller is also urgently needed for a scalable quantum computer. This study uses analytical techniques to expose the effect of nonideal circuit blocks in a classical controller on qubit fidelity, for all required operations, and how fidelity is affected by the limited performance of the general-purpose, room-temperature equipment typically used with the few qubits types available today. Tailor-made controllers can achieve significantly lower cost, power consumption, and size, as required for scaling up.