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Bulletin of the American Physical Society

Parametric Entangling Gates in a Superconducting Quantum Processor, Part III: Experiment

Shane Caldwell, Nicolas Didier, Colm A. Ryan, Eyob Alebachew Sete, Alexander Hudson, Peter J. Karalekas, Riccardo Manenti, Marcus Palmer Da Silva, Rodney Sinclair, Chad T. Rigetti

Published Mar 7, 2018• 0 citations
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Control techniques for superconducting quantum computer hardware: New radio-frequency quantum gate implementations, and electrical annealing of Josephson junctions

Christian Križan

The thesis investigates three challenges in superconducting quantum computing: efficient quantum gate compilation, scalable microwave interfacing of quantum processors (QPUs), and electrical annealing of Josephson junctions.The first part addresses an inefficiency in contemporary two-qubit gate compilation. Universal quantum computation requires only a single entangling two-qubit gate alongside single-qubit rotations, but this minimal gate set requires up to three additional two-qubit gates for every unsupported gate. I show how access to multiple inequivalent two-qubit gate classes overcomes this inefficiency. I experimentally realised an unsupported SWAP operation using one parametric CZ and one parametric iSWAP gate on a circuit-QED architecture. A Kraus-Cirac analysis shows that this combination belongs to the SWAP equivalency class, the fundamental reason for the reduction in two-qubit gates. The experiment demonstrates a rare case of simultaneous CZ and iSWAP support in the same quantum circuit, illustrating how access to multiple inequivalent gate classes can reduce compilation overhead on real hardware.The second part explores direct digital synthesis of microwave signals for interfacing with quantum processors. Conventional control uses heterodyne upconversion with IQ mixers, requiring compensation of LO leakage and IQ skew. I investigated a mixerless architecture based on high-speed DAC/ADC systems to generate and analyse the required microwave signals. CZ and iSWAP gate experiments subsequently verify that the platform is equivalent to conventional QPU setups.The third part investigates post-fabrication electrical tuning of Josephson junctions, in which voltage pulses modify junction resistance to correct fabrication-induced transmon-frequency variations. The speed of resistance change was found to depend exponentially on pulse amplitude. A novel stepwise protocol achieved a 270% resistance increase in an 11-month-old 11.5 kΩ junction, corresponding to a ~2 GHz reduction in transmon frequency, the largest reported selective resistance modification to date. Simulations show that resistance, charging-energy, and superconducting-gap uncertainties contribute equally to the uncertainty in the final qubit frequency. The results support a picture where electrical manipulation modifies the energy landscape, accelerating natural junction ageing.The thesis demonstrates that investigating gate-level compilation strategies, fully digital QPU control, and post-fabrication tuning, helps advance the understanding of how to approach scalable superconducting quantum processors.

•Oct 2, 2026•0 citations
The thesis investigates three challenges in superconducting quantum computing: efficient quantum gate compilation, scalable microwave interfacing of quantum processors (QPUs), and electrical annealing of Josephson junctions.The first part addresses an inefficiency in contemporary two-qubit gate compilation. Universal quantum computation requires only a single entangling two-qubit gate alongside single-qubit rotations, but this minimal gate set requires up to three additional two-qubit gates for every unsupported gate. I show how access to multiple inequivalent two-qubit gate classes overcomes this inefficiency. I experimentally realised an unsupported SWAP operation using one parametric CZ and one parametric iSWAP gate on a circuit-QED architecture. A Kraus-Cirac analysis shows that this combination belongs to the SWAP equivalency class, the fundamental reason for the reduction in two-qubit gates. The experiment demonstrates a rare case of simultaneous CZ and iSWAP support in the same quantum circuit, illustrating how access to multiple inequivalent gate classes can reduce compilation overhead on real hardware.The second part explores direct digital synthesis of microwave signals for interfacing with quantum processors. Conventional control uses heterodyne upconversion with IQ mixers, requiring compensation of LO leakage and IQ skew. I investigated a mixerless architecture based on high-speed DAC/ADC systems to generate and analyse the required microwave signals. CZ and iSWAP gate experiments subsequently verify that the platform is equivalent to conventional QPU setups.The third part investigates post-fabrication electrical tuning of Josephson junctions, in which voltage pulses modify junction resistance to correct fabrication-induced transmon-frequency variations. The speed of resistance change was found to depend exponentially on pulse amplitude. A novel stepwise protocol achieved a 270% resistance increase in an 11-month-old 11.5 kΩ junction, corresponding to a ~2 GHz reduction in transmon frequency, the largest reported selective resistance modification to date. Simulations show that resistance, charging-energy, and superconducting-gap uncertainties contribute equally to the uncertainty in the final qubit frequency. The results support a picture where electrical manipulation modifies the energy landscape, accelerating natural junction ageing.The thesis demonstrates that investigating gate-level compilation strategies, fully digital QPU control, and post-fabrication tuning, helps advance the understanding of how to approach scalable superconducting quantum processors.