In this paper, we study the problem Boolean function's representation in a class of reversible circuits. Each Boolean function is associated with reversible function, which is implemented by a reversible circuit. Reversible circuits are built from Toffoli elements. An operator approach is used for description of this representation. At building of reversible circuit the algorithm of finding of the minimum representation of Boolean function in a class of the extended polarized Zhegalkin polynomials is applied. The foundation of this algorithm is made by a embedding of a special operator form (SOF) of function in certain classes of operators. Previously generated library with the components corresponding to certain operators is used at construction of a Boolean function's SOF. Operators of a SOF, and the corresponding multiple-output reversible function, define the minimal reversible circuit for a given Boolean function.
In this paper, we study the problem Boolean function's representation in a class of reversible circuits. Each Boolean function is associated with reversible function, which is implemented by a reversible circuit. Reversible circuits are built from Toffoli elements. An operator approach is used for description of this representation. At building of reversible circuit the algorithm of finding of the minimum representation of Boolean function in a class of the extended polarized Zhegalkin polynomials is applied. The foundation of this algorithm is made by a embedding of a special operator form (SOF) of function in certain classes of operators. Previously generated library with the components corresponding to certain operators is used at construction of a Boolean function's SOF. Operators of a SOF, and the corresponding multiple-output reversible function, define the minimal reversible circuit for a given Boolean function.
In this paper, the problem of Boolean function's representation by the reversible circuits constructed of the Toffoli gates is considered. Interest in this problem is connected with actual studies of the possibility for realization of "cold" computations. It means that when performing such computations, there is no heat dissipation. In general, reversible circuits realize reversible functions. Therefore, Toffoli-Fredkin's method for representation of the Boolean function by the reversible function is used. In work, an algorithm for finding the minimal representation of the Boolean function in a class of the reversible circuits, which are constructed from Toffoli elements is described. The algorithm uses the polynomial normal forms or exclusive-or sum-of-products expressions (ESOPs) of the Boolean function in the operator representation and the problem of finding the minimal representation of the Boolean function in the certain class of operator bundles. The chosen class of operator bundles corresponds to a class of the extended polarized Zhegalkin polynomials, which includes a well-known class of the polarized Zhegalkin polynomials or Reed-Muller forms. In conclusion, the computational results of the algorithm for minimizing the Boolean functions in the class of reversible circuits are given.
Reversible circuits are a concrete model of reversible computation with applications in areas such as quantum computing and analysis of cryptographic block cyphers. In 1980, Toffoli showed how to realize a Boolean function by a reversible circuit, however the resulting complexity of such circuits has remained an open problem. We investigate the reversible circuit complexity of families of Boolean functions and derive conditions that characterize whether a polynomial realization is possible. First, we derive sufficient conditions on families of Boolean functions that guarantee a polynomial-size reversible circuit realization. Namely, we show that if a Boolean function can be embedded into an even parity permutation that has a polynomial-size cycle representation, then the Boolean function can be realized by a polynomial-size reversible circuit. Furthermore, we provide a construction for the realization. Second, we provide concrete realizations for several families of Boolean functions, such as the adder, incrementor, and threshold functions, which do not necessarily satisfy the preceding condition, but still have polynomial-size realizations; this is important because such realizations will necessarily form the building blocks of quantum computers.
It is a well-known fact in logic design that synthesis of some special classes of Boolean functions is often easier than the synthesis of a general unrestricted specification. In reversible logic, well-scaled synthesis methods with a reasonably small cost of the associated implementation have been found for only a few classes of functions. This includes synthesis of multiple-output symmetric and reversible linear functions. The author presents an efficient reversible/quantum synthesis method for the class of multiple-output symmetric functions. The method is purely theoretical, therefore its scaling on functions with a large number of inputs/outputs requires minimal resources. The author calculates garbage, i.e. the number of outputs that are not required by the function specification, the number of reversible gates, and the quantum cost of the presented implementations. The proposed approach is then applied to the synthesis of benchmark functions. Comparison of the designs to the previously reported implementations is favourable.
Reversible logic finds many applications, especially in the area of quantum computing. A completely specified n-input, n-output Boolean function is called reversible if it maps each input assignment to a unique output assignment and vice versa. Logic synthesis for reversible functions differs substantially from traditional logic synthesis and is currently an active area of research. The authors present an algorithm and tool for the synthesis of reversible functions. The algorithm uses the positive-polarity Reed-Muller expansion of a reversible function to synthesize the function as a network of Toffoli gates. At each stage, candidate factors, which represent subexpressions common between the Reed-Muller expansions of multiple outputs, are explored in the order of their attractiveness. The algorithm utilizes a priority-based search tree, and heuristics are used to rapidly prune the search space. The synthesis algorithm currently targets the generalized n-bit Toffoli gate library. However, other algorithms exist that can convert an n-bit Toffoli gate into a cascade of smaller Toffoli gates. Experimental results indicate that the authors' algorithm quickly synthesizes circuits when tested on the set of all reversible functions of three variables. Furthermore, it is able to quickly synthesize all four-variable and most five-variable reversible functions that were in the test suite. The authors also present results for some benchmark functions widely discussed in literature and some new benchmarks that the authors have developed. The algorithm is shown to synthesize many, but not all, randomly generated reversible functions of as many as 16 variables with a maximum gate count of 25
Abstract This paper presents a new approach to designing reversible circuits. Reversible circuits can decrease energy dissipation theoretically to zero. This feature is a base to build quantum computers. The main problem of reversible logic is designing optimal reversible circuits i.e. circuits with minimal gates number implementing the given reversible function. There are many types of reversible gates. Most popular library is a set of three types of gates so called CNT (Control, NOT and Toffoli). The method presented in this paper is based only on the Toffoli gates. A graphical representation of the reversible function called s-maps is introduced in the paper. This representation allows to find optimal reversible circuits. The paper is organized as follows. Section 1 recalls basic concepts of reversible logic. In Section 2 a graphical representation of the reversible functions is presented. Section 3 describes the algorithm whereby all optimal solutions of the given function could be obtained.
Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. Reversible logic features a one-to-one input output correspondence which makes the logic synthesis for reversible functions differs greatly from traditional Boolean functions. Exact synthesis methods can provide optimal solutions in terms of the total number of reversible gates in the synthesis results. Unfortunately, they may suffer from long computation time, due to the fact that the search space is likely to grow exponentially as the circuit size increases. Therefore, in this paper, we propose an efficient synthesis heuristic which provides high quality synthesis results of Toffoli network in more reasonable computation time. We use a weighted, directed graph for reversible function representation and complexity measurement. The proposed algorithm maximally decreases function complexity during synthesis steps. It has the ability to climb out of local minimums and guarantees algorithm convergence. The experimental results show that our algorithm can achieve optimal or very close to optimal solutions with computation time several orders of magnitude less than the exact methods. Compared with other heuristics, our method demonstrates superior performance in terms of reversible gate count as well as computation time.