Abstract Spanning a range of hardware platforms, the building-blocks of quantum processors are today sufficiently advanced to begin work on scaling-up these systems into complex quantum machines. A key subsystem of all quantum machinery is the interface between the isolated qubits that encode quantum information and the classical control and readout technology needed to operate them. As few-qubit devices are combined to construct larger, fault-tolerant quantum systems in the near future, the quantum-classical interface will pose new challenges that increasingly require approaches from the engineering disciplines in combination with continued fundamental advances in physics, materials and mathematics. This review describes the subsystems comprising the quantum-classical interface from the viewpoint of an engineer, experimental physicist or student wanting to enter the field of solid-state quantum information technology. The fundamental signalling operations of readout and control are reviewed for a variety of qubit platforms, including spin systems, superconducting implementations and future devices based on topological degrees-of-freedom. New engineering opportunities for technology development at the boundary between qubits and their control hardware are identified, transversing electronics to cryogenics.
Abstract Spanning a range of hardware platforms, the building-blocks of quantum processors are today sufficiently advanced to begin work on scaling-up these systems into complex quantum machines. A key subsystem of all quantum machinery is the interface between the isolated qubits that encode quantum information and the classical control and readout technology needed to operate them. As few-qubit devices are combined to construct larger, fault-tolerant quantum systems in the near future, the quantum-classical interface will pose new challenges that increasingly require approaches from the engineering disciplines in combination with continued fundamental advances in physics, materials and mathematics. This review describes the subsystems comprising the quantum-classical interface from the viewpoint of an engineer, experimental physicist or student wanting to enter the field of solid-state quantum information technology. The fundamental signalling operations of readout and control are reviewed for a variety of qubit platforms, including spin systems, superconducting implementations and future devices based on topological degrees-of-freedom. New engineering opportunities for technology development at the boundary between qubits and their control hardware are identified, transversing electronics to cryogenics.
Quantum computing has made significant strides, with hardware platforms now advanced enough to tackle the challenges of scaling up to larger and more robust systems. Central to this progression is the interface between quantum processors, comprising isolated qubits, and the classical systems required for their control and readout. As these systems transition from few-qubit devices to fault-tolerant architectures, the complexity of this quantum-classical interaction poses significant engineering challenges. Field-Programmable Gate Arrays (FPGAs) have emerged as an adaptable and efficient solution, offering realtime control, low-latency operations, and seamless integration. This review delves into current FPGA-based platforms, including commercial systems, as well as open-source solutions developed by academic research groups. The architecture, features, and contributions of these platforms to addressing scalability and integration issues are thoroughly examined. Additionally, the review highlights innovations in cryogeniccompatible controllers and explores the potential of Cryo-FPGAs to reduce noise and improve fidelity in quantum systems. By providing a comprehensive analysis of current technologies and identifying opportunities for advancement, this review offers valuable insights for researchers and engineers working to develop scalable quantum computing solutions.
Quantum computers have gained widespread interest as they can potentially solve problems that are intractable even for today’s supercomputers, such as the simulation of quantum systems as initially proposed by Feynman. To achieve such tremendous progress, a quantum computer relies on processing the information stored in quantum bits (qubits), the fundamental units of quantum computation, similar to the bits in a classical (i.e., non-quantum) processor. In general, a quantum processor comprising several qubits is connected through a quantum-to-classical interface consisting of classical electrical circuits for manipulating and reading out their quantum state. The accuracy of an operation on a qubit is characterized using the fidelity, which is 100 % in case of a perfect operation. In practice, a fidelity between 99 % and 99.9 % is typically achieved in today’s experiments with less than 100 qubits, limited by non-idealities in the control signals and by the implementation of the physical qubit itself. Since such qubit fidelities are too low to execute relevant quantum algorithms, quantum error correction schemes have been developed which rely on a much larger number of qubits to correct for possible errors, resulting in the need for quantum processors with thousands or millions of qubits. Solid-state qubits promise the largescale integration required to scale to millions of qubits, as they exploit the lithographic fabrication techniques borrowed from the semiconductor industry. However, state-of-theart solid-state qubits, such as transmons and single-electron spin qubits, must be typically cooled to cryogenic temperatures in a dilution refrigerator to exhibit quantum behavior. Because of the limited number of qubits (< 100) in state-of-theart solid-state quantum processors, the classical controller is currently implemented by general-purpose instruments or by tailor-made controllers operating at room temperature connected via several wires to the qubits in the cryogenic chamber. However, these systems must scale to support millions of qubits. While scaling up the underlying quantum processor is already exceptionally challenging, building the electronics required to interface such a large-scale processor is just as relevant and arduous.
Superconducting qubits based on Josephson junctions are one of the leading candidates for building a largescale quantum information processor. There have been significant advances in the performance of superconducting qubits over the past decade and there is currently rapid progress in the development of systems with up to tens of qubits. In order to build to yet larger systems, new techniques will need to be developed to address the overhead requirements for room-temperature electronics hardware and cryostat wiring for controlling and reading out large numbers of qubits. One approach to this challenge involves implementing more of the qubit control and readout in the low-temperature environment. I will describe our efforts on integrating superconducting classical digital circuitry with superconducting qubits for coherent control and readout.
The pursuit of a universal, fault-tolerant quantum computer has transformed quantum computing from a predominantly theoretical discipline into a rapidly diversifying hardware ecosystem. This review presents a comprehensive and technically grounded analysis of the principal physical qubit modalities: superconducting circuits, trapped ions, photonic platforms, neutral atoms, semiconductor spin qubits, and topological approaches, focusing on their underlying operating principles, performance characteristics, and system-level constraints. We examine how these qubit technologies are embedded within scalable quantum processor architectures, including control and readout infrastructures, connectivity topologies, and quantum error correction strategies. The review provides a comparative study of key performance metrics, such as coherence times, gate fidelities, error rates, and scalability, reveals fundamental trade-offs between speed, robustness, and operational complexity that shape distinct technological roadmaps and target applications. We further highlight the ongoing transition from noisy intermediate-scale quantum (NISQ) devices toward architectures centred on logical qubits, driven by advances in materials engineering, precision control, and quantum information theory. Together, these developments sketch the emerging routes toward fault-tolerant quantum computing and practical quantum advantage, while offering readers a coherent entry point and reference guide to the current quantum hardware landscape.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
Superconducting qubits are pivotal in advancing quantum computing, poised for scale but limited by the complexity and fidelity of their control and readout systems, relying on RF and signal processing infrastructure. This survey serves as a comprehensive and technically grounded review of control and readout architectures tailored for superconducting qubits. Synthesizing insights from device physics, circuit design, microwave engineering, signal processing, and cryogenic integration, this work details the practicalities of RF pulse generation, signal synthesis, and readout signal analysis for quantum systems. it covers key requirements, parameters, and pulse engineering techniques, including commonly used envelopes like Gaussian and DRAG designs. Moving to the system level, this survey systematically classifies and critically analyses current architectural strategies (covering key areas like frequency conversion, waveform management, and system infrastructure) and technology platforms (including adaptive classical control stacks, cryogenic CMOS circuits, and novel interconnects and interfaces), evaluating their trade-offs in performance. Extensive literature analysis identifies prevailing limitations such as wiring complexity, thermal budget constraints, latency, and power consumption, while highlighting underexplored opportunities for on-chip signal processing and novel interconnects, drawing analogies to advanced communication systems design. By consolidating diverse control paradigms and critically evaluating their trade-offs, this survey provides a unified foundation for designing next-generation quantum control stacks. Finally, a forward-looking roadmap outlines key trends in monolithic integration, cryo-compatible digital architectures, and physics-informed hardware co-design, offering both a retrospective synthesis and a prospective vision for quantum hardware engineering beyond the NISQ era.