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International Conference on Advanced Technologies for Communications

The design of optimized fast decoding protograph LDPC codes

Thuy Vu Minh Nguyen, Hieu Trung Nguyen

Published Oct 1, 2016• 13 citations
Publisher

Abstract

This paper presents a simple method of designing a protograph-based LDPC codes which has excellent performance with a small number of decoding iterations. In addition to designing LDPC codes based on the iterative decoding threshold as before, we add one more dimension into the design process which is a predefined number of decoding iterations. Simulation results show that the proposed codes have better performance than state-of-the-art protograph codes while the number of decoding iterations is small.

DOI
10.1109/atc.2016.7764790

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This paper presents a simple method of designing a protograph-based LDPC codes which has excellent performance with a small number of decoding iterations. In addition to designing LDPC codes based on the iterative decoding threshold as before, we add one more dimension into the design process which is a predefined number of decoding iterations. Simulation results show that the proposed codes have better performance than state-of-the-art protograph codes while the number of decoding iterations is small.
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This paper designs two protograph LDPC codes with code-rate R>1/2R > 1/2R>1/2. A simple method using the protograph extrinsic information transfer (PEXIT) to design the codes with a low decoding threshold and the asymptotic weight enumerator (AWE) to evaluate the error floor of the codes is deployed. Simulation results show that the proposed codes have a better error floor than prior art protograph codes and offer higher rate protographs.
In this letter, we present a design method to find good protograph-based low-density parity-check codes with the numbers of nonzero elements in the parity-check matrix and decoding iterations both strictly limited. We utilize the protograph-based extrinsic information transfer (PEXIT) analysis to evaluate the error performance and employ the differential evolution algorithm to devise a well-performed coding scheme. In particular, the number of iterations in the PEXIT analysis is set to a small value due to the limited iterations in the decoding process. Both numerical analyses and simulations verify that the resulting codes exhibit better performance than conventional code designs under the limitation of decoding complexity.
A construction method for protograph-based LDPC codes that simultaneously achieve low iterative decoding threshold and linear minimum distance is proposed. We start with a high-rate protograph LDPC code with variable node degrees of at least 3. Lower rate codes are obtained by splitting check nodes and connecting them by degree-2 nodes. This guarantees the linear minimum distance property for the lower-rate codes. Excluding checks connected to degree-1 nodes, we show that the number of degree-2 nodes should be at most one less than the number of checks for the protograph LDPC code to have linear minimum distance. Iterative decoding thresholds are obtained by using the reciprocal channel approximation. Thresholds are lowered by using either precoding or at least one very high-degree node in the base protograph. A family of high- to low-rate codes with minimum distance linearly increasing in block size and with capacity-approaching performance thresholds is presented. FPGA simulation results for a few example codes show that the proposed codes perform as predicted
In this paper we present protograph codes with a small number of degree-3 nodes and one high degree node. The iterative decoding threshold for proposed rate 1/2 codes are lower, by about 0.2 dB, than the best known irregular LDPC codes with degree at least 3. The main motivation is to gain linear minimum distance to achieve low error floor. Also to construct rate-compatible protograph-based LDPC codes for fixed block length that simultaneously achieves low iterative decoding threshold and linear minimum distance. We start with a rate 1/2 protograph LDPC code with degree-3 nodes and one high degree node. Higher rate codes are obtained by connecting check nodes with degree-2 non-transmitted nodes. This is equivalent to constraint combining in the protograph. The condition where all constraints are combined corresponds to the highest rate code. This constraint must be connected to nodes of degree at least three for the graph to have linear minimum distance. Thus having node degree at least 3 for rate 1/2 guarantees linear minimum distance property to be preserved for higher rates. Through examples we show that the iterative decoding threshold as low as 0.544 dB can be achieved for small protographs with node degrees at least three. A family of low- to high-rate codes with minimum distance linearly increasing in block size and with capacity-approaching performance thresholds is presented. FPGA simulation results for a few example codes show that the proposed codes perform as predicted.
The real application of protograph LDPC codes involves two problems: fast encoding and the encoding complexity.Protograph LDPC codes suit for fast decoding comparing with other LDPC codes,but protograph LDPC codes are not necessarily able to achieve fast encoding.The encoding of existing protograph LDPC codes is done by generate matrix,but the generate matrix of protograph LDPC codes is not sparse.Thus,protograph LDPC codes exists encoding complexity,which makes it difficult for encoder hardware implementation.In order to lower the encoding complexity of protograph LDPC codes,this paper proposes a design of multi-rate protograph LDPC codes with fast encoding;The proposed multi-rate protograph LDPC codes do not exist girth-4s;Furthermore,the fast encoding algorithms of the proposed multi-rate protograph LDPC codes can reduce encoding complexity and simplify encoder hardware.The simulation results in AWGN channels show that the BER and correct error ability performance of the proposed multi-rate protograph LDPC codes is much better than that of GB20600 LDPC codes.