Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

International ICST Conference on Communications and Networking in China

A survey of error floor of LDPC codes

Yejun He, Jie Yang, Jiawei Song

Published Aug 1, 2011• 8 citations
Publisher

Abstract

The research about error floor of finite-length LDPC code is a very hot topic recently. This survey briefly introduces the existing works in lowering and estimating error floor of LDPC codes, and sheds some light on some potential future research areas.
DOI
10.1109/chinacom.2011.6158120

Related papers

Advances of the error-floor study of LDPC codes

Jiwen Zeng

Low-density parity check(LDPC)codes are known to perform very well under iterative decoding.However,these codes often exhibit an error floor phenomenon in the high signal-to-noise(SNR)region.This paper provides a comprehensive description of the cause of the error floor phenomenon of LDPC codes.It presents a detailed description of the trapping sets,describes the methods to estimate and reduce the error floor of LDPC codes.Finally,it proposes the future development of the error floor of LDPC codes.

Information technology newsletter•Jan 1, 2009•0 citations

Error Floors of LDPC Codes

Tom Richardson

We introduce a computational technique that accurately predicts performance for a given LDPC code in the error floor region. We present some results obtained by applying the technique and describe certain aspects of it. 1

•Jan 1, 2003•686 citations

Studies on Lowering the Error Floors of Finite Length LDPC codes

Huanlin Li

Low-density parity-check (LDPC) codes can approach the Shannon limit performance closely, and are becoming one of the most promising channel codes in the Error Control Coding area.The performance of an LDPC code with given length is mainly affected by the sizes of some combinatorial characteristics of its corresponding bipartite graph and the distribution of variable degrees and check node degrees.With the help of the density evolution algorithm, randomly designed LDPC codes, with carefully chosen degree distribution pairs, have been shown to achieve better Shannon capacity performance than their regular counterparts when decoded using the iterative belief propagation (BP) decoding algorithm.However, regular LDPC codes outperform their irregular counterparts in term of their error floors.Therefore, construction of LDPC codes which have both attractive error rate performance and low error floor performance has become an attractive topic.Currently, optimization of variable node degree distribution and check node degree distribution for an LDPC code with given length, which could help the code to achieve good Shannon limit performance, has been extensively studied.In this dissertation, we demonstrate some approaches of improving the error floor performance for a given LDPC code with desired degree distribution pair.The contribution mainly includes three parts.In the first part, the relationship between cycles and unfavorable combinatorial

•Jan 1, 2011•0 citations

Error floors in LDPC codes: Fast simulation, bounds and hardware emulation

Pamela Lee, Lara Dolecek, Zhengya Zhang +3 more

Abstract — The error-correcting performance of low-density parity check (LDPC) codes, when decoded using practical iterative decoding, is known to approach Shannon limits in the asymptotic limit of large blocklengths. A substantial limitation to the use of finite-length LDPC codes is the presence of an error floor in the low frame error rate (FER) region. This paper develops a method, based on importance sampling and high SNR asymptotics as applied to suitably defined absorbing structures within the LDPC code, to predict error floors. Our results are in very close agreement with hardware-based experimental results, and moreover extend the prediction of the error probability to even lower regions. We compute both importance sampling estimates of error probabilities and deterministic estimates that are guaranteed to lower bound the error probability in the high SNR regime. I.

IEEE International Symposium on Information Theory (ISIT)•Jul 1, 2008•12 citations

Serial concatenation of reed muller and LDPC codes with low error floor

Xin Wei Xiao, Mona Nasseri, Bane V. Vasic +1 more

In this paper, we propose a concatenated coding scheme involving an outer Reed-Muller (RM) code and an inner Finite Field low-density parity check (LDPC) code of medium length and high rate. It lowers the error floor of inner Finite Field LDPC code. This concatenation scheme offers flexibility in design and it is easy to implement. In addition, the decoding works in a serial turbo manner and has no harmful trapping sets of size smaller than the minimum distance of the outer code. The simulation results indicate that the proposed serial concatenation can eliminate the dominant trapping sets of the inner Finite Field LDPC code.

Allerton Conference on Communication, Control, and Computing•Oct 1, 2017•1 citation

Analysis of decoding error probability for finite length LDPC codes ; 有限長の低密度パリティ検査符号の復号誤り率の解析

T. Nozaki, Takayuki Nozaki

•Jan 1, 2016•0 citations
Low-density parity check(LDPC)codes are known to perform very well under iterative decoding.However,these codes often exhibit an error floor phenomenon in the high signal-to-noise(SNR)region.This paper provides a comprehensive description of the cause of the error floor phenomenon of LDPC codes.It presents a detailed description of the trapping sets,describes the methods to estimate and reduce the error floor of LDPC codes.Finally,it proposes the future development of the error floor of LDPC codes.
Low-density parity-check (LDPC) codes can approach the Shannon limit performance closely, and are becoming one of the most promising channel codes in the Error Control Coding area.The performance of an LDPC code with given length is mainly affected by the sizes of some combinatorial characteristics of its corresponding bipartite graph and the distribution of variable degrees and check node degrees.With the help of the density evolution algorithm, randomly designed LDPC codes, with carefully chosen degree distribution pairs, have been shown to achieve better Shannon capacity performance than their regular counterparts when decoded using the iterative belief propagation (BP) decoding algorithm.However, regular LDPC codes outperform their irregular counterparts in term of their error floors.Therefore, construction of LDPC codes which have both attractive error rate performance and low error floor performance has become an attractive topic.Currently, optimization of variable node degree distribution and check node degree distribution for an LDPC code with given length, which could help the code to achieve good Shannon limit performance, has been extensively studied.In this dissertation, we demonstrate some approaches of improving the error floor performance for a given LDPC code with desired degree distribution pair.The contribution mainly includes three parts.In the first part, the relationship between cycles and unfavorable combinatorial
Abstract — The error-correcting performance of low-density parity check (LDPC) codes, when decoded using practical iterative decoding, is known to approach Shannon limits in the asymptotic limit of large blocklengths. A substantial limitation to the use of finite-length LDPC codes is the presence of an error floor in the low frame error rate (FER) region. This paper develops a method, based on importance sampling and high SNR asymptotics as applied to suitably defined absorbing structures within the LDPC code, to predict error floors. Our results are in very close agreement with hardware-based experimental results, and moreover extend the prediction of the error probability to even lower regions. We compute both importance sampling estimates of error probabilities and deterministic estimates that are guaranteed to lower bound the error probability in the high SNR regime. I.
In this paper, we propose a concatenated coding scheme involving an outer Reed-Muller (RM) code and an inner Finite Field low-density parity check (LDPC) code of medium length and high rate. It lowers the error floor of inner Finite Field LDPC code. This concatenation scheme offers flexibility in design and it is easy to implement. In addition, the decoding works in a serial turbo manner and has no harmful trapping sets of size smaller than the minimum distance of the outer code. The simulation results indicate that the proposed serial concatenation can eliminate the dominant trapping sets of the inner Finite Field LDPC code.