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China Communications

Partial parallel encoding and algorithmic construction of non-binary structured IRA codes

Wojciech Sułek, Marcin Kucharczyk

Published Aug 1, 2016• 3 citations
Publisher

Abstract

The non-binary (NB) Irregular Repeat Accumulate (IRA) codes, as a subclass of NB LDPC codes, potentially have an excellent error-correcting performance. They are also known to provide linear complexity of encoding, but the basic encoding method with the serial rate-1 accumulator significantly limits the encoder throughput. Then the objective of the research presented in this paper is to develop an encoding method providing significantly increased throughput of an NB-IRA encoder altogether with a flexible code construction methods for the structured (S-NB-IRA) codes eligible for the proposed encoding method. For this purpose, we reformulate the classic encoding algorithm to fit into the partial parallel encoder architecture. We propose the S-NB-IRA encoder block diagram and show that its estimated throughput is proportional to the submatrix size of the parity check matrix, which guarantees a wide complexity-throughput tradeoff. Then, in order to facilitate the S-NB-IRA coding systems design, we present a computer search algorithm for the construction of good S-NB-IRA codes. The algorithm aims at optimizing the code graph topology along with selecting an appropriate non-binary elements in the parity check matrix. Numerical results show that the constructed S-NB-IRA codes significantly outperform the binary IRA and S-IRA codes, while their performance is similar to the best unstructured NB-LDPC codes.

DOI
10.1109/cc.2016.7563713

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The non-binary (NB) Irregular Repeat Accumulate (IRA) codes, as a subclass of NB LDPC codes, potentially have an excellent error-correcting performance. They are also known to provide linear complexity of encoding, but the basic encoding method with the serial rate-1 accumulator significantly limits the encoder throughput. Then the objective of the research presented in this paper is to develop an encoding method providing significantly increased throughput of an NB-IRA encoder altogether with a flexible code construction methods for the structured (S-NB-IRA) codes eligible for the proposed encoding method. For this purpose, we reformulate the classic encoding algorithm to fit into the partial parallel encoder architecture. We propose the S-NB-IRA encoder block diagram and show that its estimated throughput is proportional to the submatrix size of the parity check matrix, which guarantees a wide complexity-throughput tradeoff. Then, in order to facilitate the S-NB-IRA coding systems design, we present a computer search algorithm for the construction of good S-NB-IRA codes. The algorithm aims at optimizing the code graph topology along with selecting an appropriate non-binary elements in the parity check matrix. Numerical results show that the constructed S-NB-IRA codes significantly outperform the binary IRA and S-IRA codes, while their performance is similar to the best unstructured NB-LDPC codes.
This paper is concerned with the construction of a class of nonbinary irregular repeat accumulate (IRA) codes. Since they are defined on the finite field GF(q) (q>2), we will refer to the constructed codes as q-ary IRA (QIRA) codes. While preserving the excellent error correcting capability of q-ary LDPC codes, QIRA codes can be efficiently encoded like conventional binary IRA codes. By adopting the progressive edge growth (PEG) algorithm to construct the parity check matrices, we can achieve the increased girth of their factor graphs and improved decoding performance. Simulation results show that, using the sum-product algorithm on GF(q), QIRA codes outperform binary LDPC codes and turbo codes in terms of bit error ratio and frame error ratio on AWGN channels. Especially, they could achieve excellent error performance when combined with high order modulations. Feasibility study indicates, with the use of the extended min-sum (EMS) decoding algorithm, QIRA codes are competitive candidates for practical applications.
Low-density parity-check (LDPC) codes have been intensively studied in the past decade for their capacity-approaching performance. LDPC code implementation complexity and the error-rate floor are still two significant unsolved issues which prevent their application in some important communication systems. In this dissertation, we make efforts toward solving these two problems by introducing the design of a class of LDPC codes called structured irregular repeat-accumulate (S-IRA) codes. These S-IRA codes combine several advantages of other types of LDPC codes, including low encoder and decoder complexities, flexibility in design, and good performance on different channels. It is also demonstrated in this dissertation that the S-IRA codes are suitable for rate-compatible code family design and a multi-rate code family has been designed which may be implemented with a single encoder/decoder.The study of the error floor problem of LDPC codes is very difficult because simulating LDPC codes on a computer at very low error rates takes an unacceptably long time. To circumvent this difficulty, we implemented a universal quasi-cyclic LDPC decoder on a field programmable gate array (FPGA) platform. This hardware platform accelerates the simulations by more than 100 times as compared to software simulations. We implemented two types of decoders with partially parallel architectures on the FPGA: a circulant-based decoder and a protograph-based decoder. By focusing on the protograph-based decoder, different soft iterative decoding algorithms were implemented. It provides us with a platform for quickly evaluating and analyzing different quasi-cyclic LDPC codes, including the S-IRA codes. A universal decoder architecture is also proposed which is capable of decoding of an arbitrary LDPC code, quasi-cyclic or not. Finally, we studied the low-floor problem by focusing on one example S-IRA code. We identified the weaknesses of the code and proposed several techniques to lower the error floor. We successfully demonstrated in hardware that it is possible to lower the floor substantially by encoder and decoder modifications, but the best solution appeared to be an outer BCH code.
Inspired by recently proposed accumulate-repeat-accumulate (ARA) codes, in this paper we propose a construction method for LDPC codes using simple loop-free encoding modules. Such codes can be viewed as serial/parallel concatenations of simple modules such as accumulators, repetition codes, differentiators, and punctured single parity check codes. Examples are accumulate-repeat-accumulate (ARA) codes, accumulate-repeat-accumulate-accumulate (ARAA) codes and accumulate-repeat-check-accumulate codes, and other variations. These codes constitute a subclass of LDPC codes with very fast encoder structure. They also have a projected graph or protograph representation that allows for high-speed decoder implementation. Based on density evolution, we show through some examples that low iterative decoding thresholds close to the channel capacity limits can be achieved with low maximum variable node degrees, as the block size goes to infinity. The decoding threshold in many examples outperforms that of the best known unstructured irregular LDPC codes constrained to have the same maximum node degree. Furthermore, by puncturing the accumulator modules, any desired higher rate codes can be obtained with thresholds that stay close to their respective channel capacity thresholds uniformly.
Low Density Parity Check (LDPC) codes over nonbinary Galois Fields GF(q) are a generalization of the industrial standard binary LDPC codes for forward error correction in communication and information systems.The nonbinary codes can achieve significantly better performance for short and moderate block lengths.A lot of works concerning "good" LDPC codes parity check matrix construction has been published so far.However, it is well known that efficient partially parallel hardware decoder architectures are allowed only for codes with blockwise partitioned structure of the parity check matrix, called structured codes.In this paper we present a versatile algorithm for construction of codes that are both nonbinary and structured.The proposed algorithm aims at optimizing the code graph (Tanner graph) by reducing the existence of small cycles with low external connectivity, while at the same time selecting appropriate nonzero coefficients from the Galois Field under interest.The algorithm can be used for code construction of any field order, block length and code rate.
The field of error correcting codes was revolutionized by the introduction of turbo codes [7] in 1993. These codes demonstrated dramatic performance improvements over any previously known codes, with significantly lower complexity. Since then, much progress has been made towards understanding the performance of these codes, as well as in using this understanding to design even better codes. This thesis takes a few more steps in both these directions. We develop a new technique, called the typical set bound, for analyzing the asymptotic performance of code ensembles based on their weight enumerators. This technique yields very tight bounds on the maximum-likelihood decoding threshold of code ensembles, and is powerful enough to reproduce Shannon's noisy coding theorem for the class of binary-input symmetric channels. We also introduce a new class of codes called irregular repeat-accumulate~(IRA) codes, which are adapted from the previously known class of repeat-accumulate~(RA) codes. These codes are competitive in terms of decoding performance with the class of irregular low-density parity-check~(LDPC) codes, which are arguably the best class of codes known today, at least for long block lengths. In addition, IRA codes have a significant advantage over irregular LDPC codes in terms of encoding complexity. We also derive an analytical bound regarding iterative decoding thresholds of code ensembles on general binary-input symmetric channels, an area in which theoretical results are currently lacking