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Quantum mechanical computers with single atom and photon fields

Kazuhiro Igeta, Y. Yamamoto

Published Jul 18, 1988• 7 citations
OpenAlex

Abstract

The physical foundation of a computer, specifically, the thermodynamic and quantum mechanical limits, has been an interesting theoretical subject for many years. The uncertainty relation between information and energy, exemplified by Maxwell’s demon1), suggests that there exists a fundamental limit on minimum energy cost per unit of information processing. The most important development in this field in the last ten years has been a reversible logic proposed by Fredkin and Toffoh2).

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Many of the fundamental limits on information processing, from thermodynamics, relativity, and quantum mechanics, are only a few decades away. Novel physically motivated computing paradigms, such as reversible computing and quantum computing, may help in certain ways, but even they remain subject to some basic limits. One can arrive at several firm conclusions regarding upper bounds on the limits of computing. In this article, the author only reviews the fundamental technology-independent limits.

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The relation between entropy and information has great significance for computation. Based on the strict reversibility of the laws of microphysics, Landauer (1961), Bennett (1973), Priese (1976), Fredkin and Toffoli (1982), Feynman (1985) and others envisioned a reversible computer that cannot allow any ambiguity in backward steps of a calculation. It is this backward capacity that makes reversible computing radically different from ordinary, irreversible computing. The proposal aims at a higher kind of computer that would give the actual output of a computation together with the original input, with the absence of a minimum energy requirement. Hence, information retrievability and energy efficiency due to diminished heat dissipation are the exquisite tasks of quantum computer technology.

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Design and Implementation of a Single-Bit Fault Detecting Reversible Arithmetic Logic Unit Using Fredkin and CNOT Gates

Sandyarani Merugu, Devisingh

Reduction in dimensions of CMOS technology has resulted in great increase in computing speeds but, at the same time, higher power consumption. Thus, a serious limitation arises since conventional approaches will eventually hit the physical limit [1], [2]. Reversible computing seems promising in the context of VLSI. In theory, it could operate without any energy loss due to lossless information processing [3], [4]. The paper presents development and implementation of a reversible Arithmetic Logic Unit (ALU) based on quantum logic gates working with qubits. The architecture is based on Fredkin gates (quantum cost 5) and CNOT gates (quantum cost 1), both preserving parity and being inherently reversible. The ALU can execute all arithmetic and logical operations and reconfigure operations dynamically according to system requirements. Also, the designed ALU possesses an inherent parity-preserving fault detection mechanism for reliable identification of single-bit faults. Overall the implemented ALU contains 9 CNOT and 7 Fredkin gates resulting in quantum cost equal to 44 and 12 garbage outputs. Thus, the quantum cost and garbage outputs are significantly lower than usual ones for the design of a reversible ALU, which generally amount to 48–65 and 16–20 correspondingly. The designed architecture is described in details through the application of Verilog HDL and simulation in Xilinx Vivado toolset. The work concentrates on optimization of such important parameters as the number of gates, quantum cost, garbage outputs, and constant inputs. Those design parameters are critical in order to develop scalable and sustainable quantum and low-power VLSI architectures.

International journal of engineering science and advanced technology.•Jun 26, 2026•0 citations

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As already emphasized in Chap. 4 information is physical and the limits to information processing tasks are ultimately set by the underlying physical laws. For instance, the standing models of computation are based on the physics of deterministic and/or stochastic classical processes; instead, quantum computation theory [84, 90, 156, 198, 266] studies the new possibilities offered by a model of computation based on quantum mechanical laws. The birth of such a theory finds a technological motivation in the high pace at which chip miniaturization proceeds.

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Implementing the Asynchronous Reversible Computing Paradigm in Josephson Junction Circuits.

Michael P. Frank

An important figure of merit for practical computing systems is energy-delay efficiency, which characterizes the number of operations a given device can perform per unit energy dissipated, per unit time taken for the operation.This efficiency metric appears to be limited in existing superconducting logic styles, motivating the search for novel, potentially more efficient forms of superconducting logic.One path to improving efficiency might be if we could remove the need for external control driven by slow clocks that is present in existing adiabatic SCE logic styles such as AQFP/RQFP.The Asynchronous Ballistic Reversible Computing (ABRC) paradigm offers an alternative model for ballistic, data-driven reversible computation.In an ongoing project at Sandia, we are attempting to demonstrate how the ABRC model can be implemented using Josephson junction circuits, while minimizing the energy-delay product.In this talk, we review the progress that has been made to date in this effort.An interesting direction for future research is to design physical mechanisms that explicitly invoke quantum processes exhibiting superadiabaticity (a.k.a."shortcuts to adiabaticity") to improve energy-delay efficiency in concrete computing technologies.We briefly review what is known about the potential applicability and limits of this approach.Dissipation-delay Efficiency (DdE) Sandia National Laboratories • The key motivating Figure of Merit (FOM) in the present study.• For a single primitive transition of the digital state of a system between two distinct informational states, consider:• The energy dissipation D incurred by that transition process.Relates to costs associated with supply of energy and cooling.• The delay d, defined as the time interval from start to end of process.Relates to costs associated with achieving a given level of parallel performance.• Then define the dissipation-delay product DdP = D • d.• Note that since refers specifically to energy dissipation, not to energy invested in the signal, in reversible processes, it is not subject to the "quantum speed limit" (QSL) lower bound of -h!No fundamental lower bound to DDP is yet known!-In fact, it would be identically zero for any perfectly-known unitary time-evolution.• Of even more general interest than DdP per se is dissipation as a function of delay, D(d), considered over a range of practical (tolerable) delay values... We'd like to extend the pareto frontier of this function within the useful range.• Dissipation-delay efficiency (DdE) of a computing technology just refers to the reciprocal of DdP, r/Dd = (Dd)-i.

•Jul 29, 2020•1 citation
The physical foundation of a computer, specifically, the thermodynamic and quantum mechanical limits, has been an interesting theoretical subject for many years. The uncertainty relation between information and energy, exemplified by Maxwell’s demon1), suggests that there exists a fundamental limit on minimum energy cost per unit of information processing. The most important development in this field in the last ten years has been a reversible logic proposed by Fredkin and Toffoh2).
Many of the fundamental limits on information processing, from thermodynamics, relativity, and quantum mechanics, are only a few decades away. Novel physically motivated computing paradigms, such as reversible computing and quantum computing, may help in certain ways, but even they remain subject to some basic limits. One can arrive at several firm conclusions regarding upper bounds on the limits of computing. In this article, the author only reviews the fundamental technology-independent limits.
The relation between entropy and information has great significance for computation. Based on the strict reversibility of the laws of microphysics, Landauer (1961), Bennett (1973), Priese (1976), Fredkin and Toffoli (1982), Feynman (1985) and others envisioned a reversible computer that cannot allow any ambiguity in backward steps of a calculation. It is this backward capacity that makes reversible computing radically different from ordinary, irreversible computing. The proposal aims at a higher kind of computer that would give the actual output of a computation together with the original input, with the absence of a minimum energy requirement. Hence, information retrievability and energy efficiency due to diminished heat dissipation are the exquisite tasks of quantum computer technology.
Reduction in dimensions of CMOS technology has resulted in great increase in computing speeds but, at the same time, higher power consumption. Thus, a serious limitation arises since conventional approaches will eventually hit the physical limit [1], [2]. Reversible computing seems promising in the context of VLSI. In theory, it could operate without any energy loss due to lossless information processing [3], [4]. The paper presents development and implementation of a reversible Arithmetic Logic Unit (ALU) based on quantum logic gates working with qubits. The architecture is based on Fredkin gates (quantum cost 5) and CNOT gates (quantum cost 1), both preserving parity and being inherently reversible. The ALU can execute all arithmetic and logical operations and reconfigure operations dynamically according to system requirements. Also, the designed ALU possesses an inherent parity-preserving fault detection mechanism for reliable identification of single-bit faults. Overall the implemented ALU contains 9 CNOT and 7 Fredkin gates resulting in quantum cost equal to 44 and 12 garbage outputs. Thus, the quantum cost and garbage outputs are significantly lower than usual ones for the design of a reversible ALU, which generally amount to 48–65 and 16–20 correspondingly. The designed architecture is described in details through the application of Verilog HDL and simulation in Xilinx Vivado toolset. The work concentrates on optimization of such important parameters as the number of gates, quantum cost, garbage outputs, and constant inputs. Those design parameters are critical in order to develop scalable and sustainable quantum and low-power VLSI architectures.
As already emphasized in Chap. 4 information is physical and the limits to information processing tasks are ultimately set by the underlying physical laws. For instance, the standing models of computation are based on the physics of deterministic and/or stochastic classical processes; instead, quantum computation theory [84, 90, 156, 198, 266] studies the new possibilities offered by a model of computation based on quantum mechanical laws. The birth of such a theory finds a technological motivation in the high pace at which chip miniaturization proceeds.
An important figure of merit for practical computing systems is energy-delay efficiency, which characterizes the number of operations a given device can perform per unit energy dissipated, per unit time taken for the operation.This efficiency metric appears to be limited in existing superconducting logic styles, motivating the search for novel, potentially more efficient forms of superconducting logic.One path to improving efficiency might be if we could remove the need for external control driven by slow clocks that is present in existing adiabatic SCE logic styles such as AQFP/RQFP.The Asynchronous Ballistic Reversible Computing (ABRC) paradigm offers an alternative model for ballistic, data-driven reversible computation.In an ongoing project at Sandia, we are attempting to demonstrate how the ABRC model can be implemented using Josephson junction circuits, while minimizing the energy-delay product.In this talk, we review the progress that has been made to date in this effort.An interesting direction for future research is to design physical mechanisms that explicitly invoke quantum processes exhibiting superadiabaticity (a.k.a."shortcuts to adiabaticity") to improve energy-delay efficiency in concrete computing technologies.We briefly review what is known about the potential applicability and limits of this approach.Dissipation-delay Efficiency (DdE) Sandia National Laboratories • The key motivating Figure of Merit (FOM) in the present study.• For a single primitive transition of the digital state of a system between two distinct informational states, consider:• The energy dissipation D incurred by that transition process.Relates to costs associated with supply of energy and cooling.• The delay d, defined as the time interval from start to end of process.Relates to costs associated with achieving a given level of parallel performance.• Then define the dissipation-delay product DdP = D • d.• Note that since refers specifically to energy dissipation, not to energy invested in the signal, in reversible processes, it is not subject to the "quantum speed limit" (QSL) lower bound of -h!No fundamental lower bound to DDP is yet known!-In fact, it would be identically zero for any perfectly-known unitary time-evolution.• Of even more general interest than DdP per se is dissipation as a function of delay, D(d), considered over a range of practical (tolerable) delay values... We'd like to extend the pareto frontier of this function within the useful range.• Dissipation-delay efficiency (DdE) of a computing technology just refers to the reciprocal of DdP, r/Dd = (Dd)-i.