In this paper we present our experience in quantum circuits design automation on the example of quantum symbolic model for Quantum Fourier transform (QFT). The lexeme set for base gates is introduced. Our quantum circuit verification by means of lexical analyzer is represented.
Abstract With the race to build large‐scale quantum computers and efforts to exploit quantum algorithms for efficient problem solving in science and engineering disciplines, the requirement to have efficient and scalable verification methods are of vital importance. A novel formal verification method that is targeted at Quantum Fourier Transform (QFT) circuits is proposed. Quantum Fourier Transform is a fundamental quantum algorithm that forms the basis of many quantum computing applications. The verification method employs abstractions of quantum gates used in QFT that leads to a reduction of the verification problem from Hilbert space to the quantifier free logic of bit‐vectors. Very efficient decision procedures are available to reason about bit‐vectors. Therefore, this method is able to scale up to the verification of QFT circuits with 10,000 qubits and 50 million quantum gates, providing a meteoric advance in the size of QFT circuits thus far verified using formal verification methods.
With the rapid development of quantum computing, automatic verification of quantum circuits becomes more and more important. While several decision diagrams (DDs) have been introduced in quantum circuit simulation and verification, none of them supports symbolic computation. Algorithmic manipulations of symbolic objects, however, have been identified as crucial, if not indispensable, for several verification tasks. This paper proposes the first decision-diagram approach for operating symbolic objects and verifying quantum circuits with symbolic terms. As a notable example, our symbolic tensor decision diagrams (symbolic TDD) could verify the functionality of the 160-qubit quantum Fourier transform circuit within three minutes. Moreover, as demonstrated on Bernstein-Vazirani algorithm, Grover's algorithm, and the bit-flip error correction code, the symbolic TDD enables efficient verification of quantum circuits with user-supplied oracles and/or classical controls.
Quantum mechanics based computing systems are expected to have high capabilities and are considered good candidates to replace classical cryptography and supercomputing systems. Among many implementations, quantum optics systems provide a promising platform to implement universal quantum computers, since they link quantum computation and quantum communication in the same framework. Recently, several quantum gates, circuits, and protocols have been experimentally realized using optics. Despite the fact that big advances in building the physical quantum computers were achieved, there are no currently available industrial computer aided tools that can perform the modeling, analysis, and verification of optical quantum computing systems. In this thesis, we tackle the idea of design automation for quantum circuits, where we use a sound language, higher order logic, to model and reason about quantum circuits formally. In particular, we propose a framework for the hierarchical modeling and automated verification of quantum computing circuits. The modeling approach captures quantum models built hierarchically from quantum gates, which models are readily available in a library. The analysis and verification of composed circuits is done seamlessly based on dedicated mathematical foundations formalized in the theorem prover. \nSpecifically, the tensor product and linear projection are used to extract the quantum circuit outputs. Subsequently, a rich library of quantum gates which includes 1-qubit, 2-qubit, and 3-qubit gates is formalized. In order to automate the analysis process, we developed a decision procedure to eliminate the need of user guidance throughout the formal proofs. To demonstrate the effectiveness of the proposed framework, we conduct the formal analysis of a benchmark of quantum circuits including the Shor's integer factorization algorithm, the Grover's oracle, and the quantum full adder.
ABSTRACT- This paper presents an integrated framework for the automated verification and visualization of quantum circuits, addressing the critical need for reliable quantum software development tools. We implement and analyze eight fundamental quantum circuits Bell states, GHZ states, Quantum Fourier Transform (QFT), Grover's search algorithm, the Variational Quantum Eigensolver (VQE) for H₂ molecules, Quantum Teleportation, Superdense Coding, and the Bernstein-Vazirani algorithm through a comprehensive verification pipeline. The system generates publication-ready circuit diagrams and performs formal verification via automated theorem proving, achieving an overall verification success rate of 93.7% across all circuits. Notably, basic circuits such as Bell and GHZ states achieve perfect verification (100% success), whereas the Quantum Teleportation circuit presents the greatest challenge, attaining only 88.9% success. Results demonstrate a strong linear correlation (R² = 0.89) between circuit complexity (gate count) and verification time, with the framework processing 348 verification conditions per second. This work establishes quantitative benchmarks for quantum software verification, highlights specific gaps in protocol-level verification, and provides an integrated toolset that bridges the gap between circuit visualization and formal correctness assurance, thereby advancing the state of quantum software engineering.
Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.