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Journal of Nantong University

Couting and Cascading of Toffoli Gate Reversible Networks

Ming-Qiang Xu

Published Jan 1, 2010• 0 citations
OpenAlex

Abstract

The relationship between the output and the gate number for the same type of Toffoli gates in series was analyzed and proved.In order to ensure the convergence in the process of series connection,we gave the method of calculating the number of the reversible network cascaded by Toffoli gates and proved the relationship between the bit vector′s number of Hamming weight and the number of input/output.An algorithm on how to get a cascade network in series,parallel and mixture based on Toffoli gates was proposed and its validity was further verified.

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The relationship between the output and the gate number for the same type of Toffoli gates in series was analyzed and proved.In order to ensure the convergence in the process of series connection,we gave the method of calculating the number of the reversible network cascaded by Toffoli gates and proved the relationship between the bit vector′s number of Hamming weight and the number of input/output.An algorithm on how to get a cascade network in series,parallel and mixture based on Toffoli gates was proposed and its validity was further verified.
This paper analyzes and proves that the relationship between the output results of the homotypic Toffoli gate which is series cascade and the number of the gates which are series cascade. In order to guarantee the convergence of the process of the series cascade, we gave the counting results of the series cascade network for Toffoli gates, and proved that in the input vector (0, 1, …, 2n-1), the number of the bit vectors with Hamming weight H(w)≥n-1 is equal to the bit number of bit vectors plus 1, and obtained the conclusion that there are (n+1)! kinds of transformation for Toffoli gate series cascade network. Simultaneously we provide the series cascade network algorithm of the Toffoli gates. The reversible network cascade system designed by the above algorithm verified the validity of this algorithm.
This paper analyzes and proves that the relationship between the output results of the homotypic Toffoli gate, which is series cascade and the number of the gates. In order to guarantee the convergence of the process of the series cascade, we gave the counting results of the series cascade network for Toffoli gates, and proved that the number of the bit vectors with Hamming weight H(w)≥ n-1 is equal to the bit number of bit vectors plus 1, and obtained the conclusion that there are (n+1)! kinds of transformation for Toffoli gate series cascade network. Simultaneously we provide the series cascade network algorithm of the Toffoli gates. The reversible network cascade system designed by the above algorithm verified the validity of this algorithm.
A reversible logic function maps each of the 2m input patterns to a unique output pattern. The network cascade structure problem is to realize a reversible function by a cascade of primitive reversible gates. We present a method that synthesizes a network with family of Toffoli gates. The cascade algorithm finds cascade of Toffoli gates with no backtracking and minimal look-ahead, and apply transformations that reduce the number of gates in the network. We have synthesized all three input and output reversible functions and compare our results to the other optimal results. We also present the results of applying our synthesis method to obtain networks for number of benchmark function.
Reversible computing is an emerging area of research.The reversible logic gate cascade is the important composition parts of the reversible logic synthesis.This paper proposed the reversible logic gate network cascade method-based the reversible logic gate coding and the variable system numbers,which can generate single reversible network or the batching continuous sequence numbers reversible network.Via the corresponding relationship between the variable system numbers and reversible network output vectors,we can locate quickly the corresponding sequence numbers of the reversible network output vectors and judge preciously whether the output vectors have been appeared meanwhile reducing the times of search and search space.Compared with examples of the benchmark,the number of control-bits and the number of the reversible logic gates has been improved to some degree.
Optimization of reversible circuits is one of key problems of reversible logic synthesis.To solve the problem of high algorithm complexity and poor scalability of reversible Toffoli circuits,the paper analyzed and summarized relationship between adjacent Toffoli gates,proposed and proven the moving and simplification rules of sub-sequence of reversible circuit cascaded by Toffoli gates,and gave the optimization algorithm based on these rules.The algorithm examines the circuit bidirectionally according to the moving rules,searches the sub-sequence satisfying simplification rules,performs corresponding optimization,and the process is repeated until the circuit does' t change.The algorithm is irrelevant to the number of input lines,does' t need to store extra information,is suitable to different Toffoli circuit synthesis methods,and its algorithm complexity is O(s3),which is superior to O(n!t2s3)of generally used template optimization technique.Results of examples and experiments on all 3-bit reversible functions show that the number of gates and the control bits can be reduced effectively and the cost of reversible circuit is decreased.
Reversible calculating is an emerging area of research and reversible logic synthesis is its important aspect. This paper proposed the reversible logic gate network cascade method-based the variable system numbers, which can generate single reversible network or the batching continuous sequence numbers reversible network. Via the corresponding relationship between the variable system numbers and reversible network output vectors, we can locate quickly the corresponding sequence numbers of the reversible network output vectors and judge preciously whether the output vectors have been appeared meanwhile reducing the times of search and search space. Compared with examples of the benchmark, the number of control-bit and the number of the reversible logic gates have been improved to some degree.