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IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC)

The improved Turbo-decoding Message-passing algorithm and corresponding decoder for LDPC based on LTE

Lingling Lao, Lixin Li, Zhu Meng, Huisheng Zhang

Published Aug 1, 2014• 6 citations
Publisher

Abstract

The Turbo-decoding Message-passing (TDMP) algorithm of Low-Density Parity-Check (LDPC) codes has a faster convergence speed, lower hardware implementation complexity, and less storage units than the Belief-Passing (BP) algorithms. However, because of the integer quantization operations for initial information, restriction of storage units will cause the problem of decoding information overflowing. This paper gives the reason of overflow errors, proposes the improved decoding algorithm which can partially eliminate overflow errors, and designs the corresponding decoder which only requires some extra subtractors and shift operations. We analyze the computation complexity and compute decoder throughput. Finally, we simulate the error performances of the LDPC codes over the LTE channel, and simulation results show that the proposed algorithm effectively suppresses the overflow errors with a low decoder complexity and a high throughput.

DOI
10.1109/icspcc.2014.6986326

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The Turbo-decoding Message-passing (TDMP) algorithm of Low-Density Parity-Check (LDPC) codes has a faster convergence speed, lower hardware implementation complexity, and less storage units than the Belief-Passing (BP) algorithms. However, because of the integer quantization operations for initial information, restriction of storage units will cause the problem of decoding information overflowing. This paper gives the reason of overflow errors, proposes the improved decoding algorithm which can partially eliminate overflow errors, and designs the corresponding decoder which only requires some extra subtractors and shift operations. We analyze the computation complexity and compute decoder throughput. Finally, we simulate the error performances of the LDPC codes over the LTE channel, and simulation results show that the proposed algorithm effectively suppresses the overflow errors with a low decoder complexity and a high throughput.
In this paper, we propose a turbo decoding message-passing (TDMP) algorithm to decode regular and irregular low-density parity-check (LDPC) codes. The TDMP algorithm has two main advantages over the commonly employed two-phase message-passing algorithm. First, it exhibits a faster convergence behavior (up to 50% less iterations), and improvement in coding gain (up to an order of magnitude for moderate-to-high SNR and small number of iterations). Second, the corresponding decoder architecture has a significantly reduced memory requirement that amounts to a savings of (75 + 25n//spl Sigma/ node-degrees)% > 75% for code-length n. A decoder architecture featuring the TDNW algorithm is also presented. Furthermore, we propose a new structure on the parity-check matrix of an LDPC code based on permutation matrices aimed at reducing interconnect complexity and improving decoding throughput. In addition, we construct a wide range of LDPC codes based on Ramanujan graphs which possess this structure.
Much attention has been paid recently to the so-called layered decoding of LDPC codes, also known as turbo-decoding message passing (TDMP). The TDMP algorithm for decoding LDPC codes is known to possess some desirable features, such as fast convergence speed, reduced memory requirements and reduced implementation complexity in comparison with standard two-phase message passing algorithm. In this paper we analyze an important issue connected with hardware implementation of TDMP algorithm, namely the finite precision representation of messages influence on the decoding performance. Constrained dynamic range of the finite precision representation of messages entails overflow errors. We present an analysis revealing that in the subsequent decoding iterations, the subtraction of non-overflowed intrinsic message from overflowed extrinsic message is a source of errors that have substantial impact on the decoding results. The analysis is confirmed by simulation results showing significant performance loss. However this performance loss can be almost completely eliminated with a basic modifications in the messages computation algorithm. Effectiveness of the presented modifications is confirmed by simulation results obtained with hardware TDMP decoder implementation that has been developed.
Terrestrial digital multimedia TV/handle broadcasting (DMB-TH) is a newly upcoming framing structure, channel coding and modulation for digital television terrestrial broadcasting system standard of China, which is recently drafted and is ready to be verified in order to deploy mobile multimedia broadcasting services for the public. The adoption of strong channel coding techniques appears to be of key importance for mobile operators and broadcasters. Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presents a turbo-decoding message-passing algorithm (TDMP) based LDPC code search algorithm with hardware considerations. The main advantages of the proposed algorithm over the DMB-TH standard decoding algorithm are 1) improvement in coding gain by an order of magnitude at high signal-to-noise ratio (SNR), 2) reduced decoder complexity. The performance of the proposed TDMP architecture is shown by the comparison of simulation results.
A turbo-decoding message-passing (TDMP) algorithm for sparse parity-check matrix (SPCM) codes such as low-density parity-check, repeat-accumulate, and turbo-like codes is presented. The main advantages of the proposed algorithm over the standard decoding algorithm are 1) its faster convergence speed by a factor of two in terms of decoding iterations, 2) improvement in coding gain by an order of magnitude at high signal-to-noise ratio (SNR), 3) reduced memory requirements, and 4) reduced decoder complexity. In addition, an efficient algorithm for message computation using simple “max” operations is also presented. Analysis using EXIT charts shows that the TDMP algorithm offers a better performance–complexity tradeoff when the number of decoding iterations is small, which is attractive for high-speed applications. A parallel version of the TDMP algorithm in conjunction with architecture-aware (AA) SPCM codes, which have embedded structure that enables efficient high-throughput decoder implementation, are presented. Design examples of AA-SPCM codes based on graphs with large girth demonstrate that AA-SPCM codes have very good error-correcting capability using the TDMP algorithm.
Based on density evolution analysis of the existing belief propagation (BP) algorithm, the Turbo Decoding Message Passing (TDMP) algorithm was analyzed from the perspective of density evolution and Gaussian approximation, and the theoretical analysis process of TDMP algorithm was given. When calculating the prior message of each layer of the TDMP algorithm, the check message of the previous iteration should be subtracted. Therefore, the result will not be convergent, if the TDMP algorithm is directly analyzed based on density evolution and Gaussian approximation. We researched the TDMP algorithm based on the symmetry conditions to obtain the convergent result. When using density evolution (DE) and Gaussian approximation to analyze the decoding convergence of the TDMP algorithm, we can provide a theoretical basis for proving the superiority of the algorithm. Then, based on the DE theory, we calculated the probability density function (PDF) of the check-to-variable information of TDMP and its simplified algorithm, and then gave it a calculation based on the process of the normalization factor. Simulation results show that the decoding convergence speed of the TDMP algorithm was faster and the iterations were smaller compared to the BP algorithm under the same conditions.
The common approach for the design of an error correction system is first to construct a code and then to define the hardware structure of the encoder and decoder. However, in the case of LDPC codes (low-density parity-check) such a constructed code is generally not well suited for a hardware implementation. It has been recognized that the code construction and hardware design must be considered jointly to facilitate LDPC decoder and encoder implementation. In this paper, an efficient decoder structure for regular and irregular LDPC codes, based on TDMP (turbo-decoding message passing) scheme is designed first. The decoder has been implemented and verified in an FPGA device. Constraints for the parity check matrix of a code to be suitable for the decoder architecture are defined. Then an algorithm for LDPC parity check matrix construction subject to these constraints is presented. The algorithm aims at improving performance of the code in the low SNR region by employing irregular codes as well as in high SNR region by reducing the number of small Stopping Sets and Trapping Sets in the Tanner graph of the code making use of a computer search technique.