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JOURNAL OF ELECTRONICS INFORMATION TECHNOLOGY

A Method for Designing Quasi-Cyclic LDPC Codes Based on Girth Optimization

Hua Xu, Chengqi Xu

Published Mar 24, 2011• 0 citations
Publisher

Abstract

在准循环LDPC码的构造中，校验矩阵拥有尽可能好的girth分布对于改善码的性能有着重要的意义。该文提出了构造准循环LDPC码的GirthOpt-DE算法，优化设计以获得具有好girth分布的移位参数矩阵为目标。仿真结果表明，该文方法得到的准循环LDPC码在BER性能和最小距离上均要优于固定生成函数的准循环LDPC码，Arrary码和Tanner码，并且使用上更为灵活，可以指定码长，码率及尽可能好的girth分布。

DOI
10.3724/sp.j.1146.2006.02002

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在准循环LDPC码的构造中，校验矩阵拥有尽可能好的girth分布对于改善码的性能有着重要的意义。该文提出了构造准循环LDPC码的GirthOpt-DE算法，优化设计以获得具有好girth分布的移位参数矩阵为目标。仿真结果表明，该文方法得到的准循环LDPC码在BER性能和最小距离上均要优于固定生成函数的准循环LDPC码，Arrary码和Tanner码，并且使用上更为灵活，可以指定码长，码率及尽可能好的girth分布。
An improved combining method is proposed for constructing quasi‐cyclic low‐density parity‐check (QC‐LDPC) codes with large girth and few short cycles. Large girth QC‐LDPC codes can be obtained by carefully designing one component code with large girth. By properly designing the other component codes, a lot of QC‐LDPC codes with very few short cycles can be designed. Simulations show that compared with Chinese remainder theorem based QC‐LDPC codes and progressive edge‐growth based QC‐LDPC codes, the proposed QC‐LDPC codes have much less short cycles and better performance.
设计的一条改进欧几里德几何学的几何学途径伪周期(质量管理) 有高率、低的错误地板的低密度的同等值检查(LDPC ) 代码被论述。构造 QC-LDPC 代码与高率比原来的代码有更低的错误地板。最小的重量 codeword 的分发被分析，并且最小的重量 codeword 的一个足够的存在条件被发现。很多 QC-LDPC 与更低的错误地板编码的模拟表演能被减少最小的重量 codewords 的数字设计令人满意这个足够的条件。
In this paper, we present an improved method for obtaining quasi-cyclic low-density parity-check (QC-LDPC) codes of larger length by combining some component QC-LDPC codes of smaller length.Large girth can be obtained by carefully designing one large girth component code of smaller length.The other component codes are properly designed to obtain a lot of QC-LDPC codes with much few short cycles.Simulations show that compared with CRT based QC-LDPC codes and PEG based QC-LDPC codes, the proposed QC-LDPC codes have much less short cycles and better performance.
We present an approach to designing capacity-approaching high-girth low-density parity-check (LDPC) codes that are friendly to hardware implementation, and compatible with some desired input code structure defined using a protograph. The approach is based on a mapping of any class of codes defined using a protograph into a family of hierarchical quasi-cyclic (HQC) LDPC codes. Whereas the parity check matrices of standard quasi-cyclic (QC) LDPC codes are composed of circulant submatrices, those of HQC LDPC codes are composed of a hierarchy of circulant submatrices that are, in turn, constructed from circulant submatrices, and so on, through some number of levels. Next, we present a girth-maximizing algorithm that optimizes the degrees of freedom within the family of codes to yield a high-girth HQC LDPC code, subject to bounds imposed by the fact that HQC codes are still quasi-cyclic. Finally, we discuss how certain characteristics of a code protograph will lead to inevitable short cycles and show that these short cycles can be eliminated using a “squashing” procedure that results in a high-girth QC LDPC code, although not a hierarchical one. We illustrate our approach with three design examples of QC LDPC codes-two girth-10 codes of rates 1/3 and 0.45 and one girth-8 code of rate 0.7-all of which are obtained from protographs of one-sided spatially coupled codes.