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Physical Review A

Robustness and performance scaling of a quantum computer with respect to a class of static defects

Yunseong Nam, R. Blümel

Published Dec 10, 2013• 8 citations
Publisher

Abstract

Competing computationally with experimental groups for the construction of scaling quantum computers, we simulate a complete quantum-gate by quantum-gate implementation of Shor's algorithm on a classical 128-core cluster computer. The resulting virtual quantum computer serves as a convenient quantum laboratory for the investigation of the effect of defects in the quantum circuitry. The class of defects studied here is the removal of all rotation gates with rotation angles $\ensuremath{\theta}<\ensuremath{\pi}/{2}^{b}$. Factoring semiprimes $N=21,33,35,39,55,57$, we find that the quantum computer still operates with acceptable performance (success probability of factoring) down to $b=2$. This is surprising since the deletion of rotation gates results in large errors in the arithmetic circuitry of the quantum computer. Extrapolating on the basis of these results we conclude that for quantum computers of practical interest more than 99% of rotation gates may be discarded with acceptable consequences in quantum computer performance. This result may be of interest to experimental physicists and quantum engineers currently embarked on designing efficient circuitry for scaling quantum computers.

DOI
10.1103/physreva.88.062310

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Competing computationally with experimental groups for the construction of scaling quantum computers, we simulate a complete quantum-gate by quantum-gate implementation of Shor's algorithm on a classical 128-core cluster computer. The resulting virtual quantum computer serves as a convenient quantum laboratory for the investigation of the effect of defects in the quantum circuitry. The class of defects studied here is the removal of all rotation gates with rotation angles \ensuremathθ<\ensuremathπ/2b\ensuremath{\theta}<\ensuremath{\pi}/{2}^{b}\ensuremathθ<\ensuremathπ/2b. Factoring semiprimes N=21,33,35,39,55,57N=21,33,35,39,55,57N=21,33,35,39,55,57, we find that the quantum computer still operates with acceptable performance (success probability of factoring) down to b=2b=2b=2. This is surprising since the deletion of rotation gates results in large errors in the arithmetic circuitry of the quantum computer. Extrapolating on the basis of these results we conclude that for quantum computers of practical interest more than 99% of rotation gates may be discarded with acceptable consequences in quantum computer performance. This result may be of interest to experimental physicists and quantum engineers currently embarked on designing efficient circuitry for scaling quantum computers.
We constructed a virtual quantum computer by running a complete, scaling, quantum-gate--by--quantum-gate implementation of Shor's algorithm on a 128-core classical cluster computer. In mode A [quantum period finding (PF) only, supplied with classical results for the modular exponentiation (ME) part of Shor's algorithm], factoring semiprimes up to N=557993N=557\phantom{\rule{0.16em}{0ex}}993N=557993 with up to n=39n=39n=39 qubits, we confirm earlier, smaller-nnn results concerning the performance scaling of Shor's algorithm equipped with a truncated (banded) quantum Fourier transform. Running our virtual quantum computer in mode B (full quantum implementation of ME and PF), we find that a large number of gates may be discarded in a scalable way in both the ME and PF parts of Shor's algorithm in exchange for only a small reduction in performance. We explicitly state the associated scaling laws. Implying significant savings in quantum gates, we suggest that these results are of importance for future experimental and technical large-nnn implementations of quantum computers.
This thesis presents an overview of my published work on streamlining and optimizing quantum processors. Complete, microscopic, quantum-gate–by–quantum-gate simulations of a variety of quantum circuits are implemented and executed on state-of-the-art multi-processor parallel computers. A host of analytical scaling formulas addressing the quality of quantum processors, e.g., in the presence of realistic gate errors and defects, are presented. These formulas reliably describe the practically interesting, large-number-of-qubit regime, inaccessible to simulations on classical computers. Much of the technical details may be found in my published articles, which appear in the Appendix. This thesis also presents the generic and specific directions into which my current investigations are headed. In addition, several preliminary results are presented and discussed.
Addressing Landauer's question concerning the influence of static gate defects on quantum information processor performance, we investigate analytically and numerically the case of the quantum Fourier transform (QFT) with defective controlled rotation (CROT) gates. Two types of defects are studied, separately and in combination: systematic and random. Analytical scaling laws of QFT performance are derived with respect to the number of qubits nnn, the size δ\deltaδ of systematic defects, and the size ϵ\epsilonϵ of random defects. The analytical results are in excellent agreement with numerical simulations. In addition, we present an unexpected result: The performance of the defective QFT does not deteriorate with increasing nnn, but approaches a constant that scales in ϵ\epsilonϵ. We derive an analytical formula that accurately reproduces the ϵ\epsilonϵ scaling of the performance plateaus. Overall, we observe that the CROT gates may exhibit static and random defects of the order of 30\% and larger, and still result in satisfactory QFT performance. Thus we answer Landauer's question in the case of the QFT: far from being lethal, the QFT can tolerate tremendous static gate defects and still perform its function. The extraordinary robustness of the QFT with respect to static gate defects displayed in our numerical and analytical calculations should be a welcome boon for laboratory and industrial realizations of quantum circuitry.
Removing a single logical gate from a classical information processor renders this processor useless. This is not so for a quantum information processor. A large number of quantum gates may be removed without significantly affecting the processor's performance. In this paper, focusing on the quantum Fourier transform (QFT) and quantum adder, we show even more: Even if most of its gates are eliminated and the remaining gates are selected from a randomly generated set, the QFT, one of the most useful quantum processors, and the quantum adder, one of the most basic building blocks of a universal quantum computer, still operate with satisfactory success probability, comparable to that of a quantum computer constructed with perfect gates. We support these conclusions by first laying out a general analytical framework and then deriving analytical scaling relations, which are in excellent agreement with our numerical simulations. The demonstrated robustness of the QFT and quantum adder, to the point where randomly generated quantum gates take the place of the exact gates, is an important boon for the construction of quantum computers, since it shows that stringent gate error tolerances do not have to be met to obtain satisfactory performance of the corresponding quantum processors. Our analytical techniques are powerful enough to generate asymptotic scaling laws for any gate defect model of quantum information processors and we illustrate this point by explicitly computing asymptotic analytical scaling formulas for several other defect models as well.
The publication in 1994 of Shor's algorithm, which allows factorisation of composite number N in a time polynomial in its binary length L has been the primary catalyst for the race to construct a functional quantum computer. However, it seems clear that any practical system that may be developed will not be able to perform completely error free quantum gate operations or shield even idle qubits from inevitable error effects. Hence, the practicality of quantum algorithms needs to be investigated to not only determine limitations on such algorithms in a noisy quantum computer, but also to estimate what demands must be made of quantum error correction (QEC). Shor's algorithm is a combination of both classical pre and post-processing, and also a quantum period finding subroutine (QPF) which allows for the exponential speed up of this algorithm on a quantum device. This paper will look at the stability of this quantum subroutine under the effects of several error models. Direct simulation of the entire QPF subroutine required to factorise a given composite number N in the presence of errors shows that the circuit required to implement Shor's algorithm is very sensitive to a small number of errors within the entire calculation. Well designed and efficient error correction codes, quick gate times and very low gate error rates will be essential for any physical realisation of Shor's factoring algorithm.
Typical circuit implementations of Shor's algorithm involve controlled rotation gates of magnitude $\ensuremath{\pi}∕{2}^{2L}$ where LLL is the binary length of the integer NNN to be factored. Such gates cannot be implemented exactly using existing fault-tolerant techniques. Approximating a given controlled $\ensuremath{\pi}∕{2}^{d}$ rotation gate to within $\ensuremath{\delta}=O(1∕{2}^{d})$ currently requires both a number of qubits and a number of fault-tolerant gates that grows polynomially with ddd. In this paper we show that this additional growth in space and time complexity would severely limit the applicability of Shor's algorithm to large integers. Consequently, we study in detail the effect of using only controlled rotation gates with ddd less than or equal to some dmax{d}_{\mathrm{max}}dmax​. It is found that integers up to length Lmax=O(4dmax){L}_{\mathrm{max}}=O({4}^{{d}_{\mathrm{max}}})Lmax​=O(4dmax​) can be factored without significant performance penalty implying that the cumbersome techniques of fault-tolerant computation only need to be used to create controlled rotation gates of magnitude $\ensuremath{\pi}∕64$ if integers thousands of bits long are desired factored. Explicit fault-tolerant constructions of such gates are also discussed.