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International Conference on Natural Computation (ICNC)

A novel method to reduce ancilla and garbage bits of reversible quantum multipliers

Zhi Wang, Shuming Chen, Wei Liu

Published Aug 1, 2015• 5 citations
Publisher

Abstract

Reversible logic is widely used in optical information processing, bioinformatics and quantum computing etc. Reversible logic requires ancilla inputs and garbage outputs to keep reversibility. However, it needs to reduce the number of these logic bits in complex designs, such as reversible quantum multipliers. In the existing literatures, researchers have optimized the multi-operand addition part and the partial product generation part of reversible quantum multipliers separately, which produce considerable overhead in terms of garbage outputs and ancilla inputs. This paper presents a novel method to reduce garbage outputs and ancilla inputs of reversible quantum multipliers. The proposed methodology converts some garbage outputs of the previous calculation to zeros, which are then served as ancilla inputs of the later calculation. In order to verify the proposed method, we apply it to two typical reversible quantum multiplier designs. Results show that the proposed method can greatly reduce the number of garbage outputs and ancilla inputs compared to the existing designs.

DOI
10.1109/icnc.2015.7378019

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Reversible logic is widely used in optical information processing, bioinformatics and quantum computing etc. Reversible logic requires ancilla inputs and garbage outputs to keep reversibility. However, it needs to reduce the number of these logic bits in complex designs, such as reversible quantum multipliers. In the existing literatures, researchers have optimized the multi-operand addition part and the partial product generation part of reversible quantum multipliers separately, which produce considerable overhead in terms of garbage outputs and ancilla inputs. This paper presents a novel method to reduce garbage outputs and ancilla inputs of reversible quantum multipliers. The proposed methodology converts some garbage outputs of the previous calculation to zeros, which are then served as ancilla inputs of the later calculation. In order to verify the proposed method, we apply it to two typical reversible quantum multiplier designs. Results show that the proposed method can greatly reduce the number of garbage outputs and ancilla inputs compared to the existing designs.
Reversible logic has emerged as a promising computing paradigm having applications in quantum computing, optical computing, dissipation less computing and low power computing etc. In reversible logic there exists a one to one mapping between the input and output vectors. Reversible circuits require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Quantum circuits of many qubits are extremely difficult to realize thus reduction in the number of ancilla inputs and the garbage outputs is the primary goal of optimization. In existing literature researchers have proposed several designs of reversible quantum multipliers based on reversible full adders and reversible half adders. The use of reversible full adders and the half adders for the addition of partial products increases the overhead in terms of number of ancilla inputs and number of garbage outputs. This paper presents a binary tree based design methodology for a NxN reversible quantum multiplier. The proposed binary tree based design methodology for NxN reversible quantum multiplier performs the addition of partial products in parallel using the reversible ripple quantum adders with no garbage output and ancilla bit, thereby minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows the improvement of 17.86% to 60.34% in terms of ancilla inputs; and 21.43% to 52.17% in terms of garbage outputs compared to all the existing reversible quantum multiplier designs.
A reversible logic has application in quantum computing. A reversible logic design needs resources such as ancilla and garbage qubits to reconfigure circuit functions or gate functions. The removal of garbage qubits and ancilla qubits are essential in designing an efficient quantum circuit. In the literature, there are multiple designs that have been proposed for a reversible multiplication operation. A multiplication hardware is essential for the circuit design of quantum algorithms, quantum cryptanalysis, and digital signal processing (DSP) applications. The existing designs of reversible quantum integer multipliers suffer from redundant garbage qubits. In this work, we propose a reversible logic based, garbage-free and ancilla qubit optimized design of a quantum integer multiplier. The proposed quantum integer multiplier utilizes a novel add and rotate methodology that is specially suitable for a reversible computing paradigm. The proposed design methodology is the modified version of a conventional shift and add method. The proposed design of the quantum integer multiplier incorporates add or no operation based on multiplier qubits and followed by a rotate right operation. The proposed design of the quantum integer multiplier produces zero garbage qubits and shows an improvement ranging from 60% to 90% in ancilla qubits count over the existing work on reversible quantum integer multipliers.
Reversible computing is an emerging field of research and has made remarkable progress. Owing to the reduced energy dissipation in reversible circuits, a lot of research has been done on the design of reversible circuits. In reversible logic circuit designs, along with primary inputs, few constant inputs (Ancilla Inputs) are used to realize required reversible functions. In addition to this, few unused or extra output bits are generated; these bits are named as Garbage Output bits. A challenge in the reversible computation is to use minimum Ancilla Inputs and generate zero Garbage Outputs. In this work, we present designs for addition, subtraction, and addition or subtraction operations. The designs are primarily optimized to achieve zero Garbage Outputs and minimum Ancilla Inputs. In addition, these proposed arithmetic circuits are designed for best Gate Count and Quantum Cost values compared to the existing counterparts.
Reversible logic is gaining significance in the context of emerging technologies such as quantum computing since reversible circuits do not lose information during computation and there is one-to-one mapping between the inputs and outputs. In this work, we present a class of new designs for reversible binary and BCD adder circuits. The proposed designs are primarily optimized for the number of ancilla inputs and the number of garbage outputs and are designed for possible best values for the quantum cost and delay. In reversible circuits, in addition to the primary inputs, some constant input bits are used to realize different logic functions which are referred to as ancilla inputs and are overheads that need to be reduced. Further, the garbage outputs which do not contribute to any useful computations but are needed to maintain reversibility are also overheads that need to be reduced in reversible designs. First, we propose two new designs for the reversible ripple carry adder: (i) one with no input carry c 0 and no ancilla input bits, and (ii) one with input carry c 0 and no ancilla input bits. The proposed reversible ripple carry adder designs with no ancilla input bits have less quantum cost and logic depth (delay) compared to their existing counterparts in the literature. In these designs, the quantum cost and delay are reduced by deriving designs based on the reversible Peres gate and the TR gate. Next, four new designs for the reversible BCD adder are presented based on the following two approaches: (i) the addition is performed in binary mode and correction is applied to convert to BCD when required through detection and correction, and (ii) the addition is performed in binary mode and the result is always converted using a binary to BCD converter. The proposed reversible binary and BCD adders can be applied in a wide variety of digital signal processing applications and constitute important design components of reversible computing.
Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.
Quantum computation is modeled by quantum circuits. All the quantum operations are reversible so the quantum circuits can be built using reversible logic gates. Reversible computing is the emerging technology, its major role is in the field of quantum computing, optical computing, and design of low power nanocircuits. The most frequently used computational unit for digital signal processing and multimedia applications is multiplier. To compute square of an operand, regular multipliers are used in general. This paper proposes a dedicated quantum circuit for computing square of an operand efficiently compared to the existing multipliers in the literature. The squaring unit is mathematically modeled and its metrics quantum cost, garbage outputs and ancilla input, gate count are calculated. We compared the proposed design with the existing multipliers to compute square and found that proposed square unit is efficient in terms of quantum cost, garbage outputs, ancilla inputs and gate count. The proposed reversible square circuit has 63% to 85% improvement of quantum cost, garbage outputs, ancilla inputs and gate count over existing reversible multiplier circuits.