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IEEE Circuits and Systems Symposium on Emerging Technologies

Low complexity decoding algorithm of parallel concatenated LDPC code

Jin Li, Xiaohu You, Yun Hee Kim

Published Nov 12, 2004• 6 citations
Publisher

Abstract

PCGC (parallel concatenated Gallager code) is a new class of concatenated codes based on component LDPC codes. The decoder of it uses modified BP (belief propagation) algorithm in component LDPC decoder. But this conventional decoding algorithm has high complexity and is not suitable for implementation in hardware. So in this paper we propose a new decoding algorithm of PCGC, which has good performance and low complexity. And it is feasible to be implemented in hardware.

DOI
10.1109/casset.2004.1322978

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PCGC (parallel concatenated Gallager code) is a new class of concatenated codes based on component LDPC codes. The decoder of it uses modified BP (belief propagation) algorithm in component LDPC decoder. But this conventional decoding algorithm has high complexity and is not suitable for implementation in hardware. So in this paper we propose a new decoding algorithm of PCGC, which has good performance and low complexity. And it is feasible to be implemented in hardware.
Parallel Concatenated Gallager Code (PCGC) is a class of concatenated error correcting codes designed to reduce the encoding and decoding complexity of long block length Low Density Parity Check (LDPC) codes. In this paper, we present a novel class of PCGC in which one constituent code satisfies zero syndrome criteria and the other one satisfies non-zero syndrome criteria. Simulation results show that proposed non-zero syndrome PCGC outperforms existing non-zero syndrome PCGC in terms of its bit error rate (BER) performance in Binary Symmetric Channel (BSC). We also show that proposed concatenation method gives better performance than dedicated LDPC of same frame length and code rate over BSC.
Weighted Erasure Decoding(WED) algorithm is investigated in this paper,based on which,a new BP-WED concatenation algorithm for LDPC codes is proposed.Belief Propagation(BP) algorithm is a kind of soft-in-soft-out algorithm.When BP algorithm fails,the soft LLR reliable information is quantized and sent to the WED algorithm.WED algorithm is a very attractive solution for practical implementations of low-complexity reliability-based algorithms owing to its simplicity,therefore the BP-WED concatenation algorithm is more easy in hardware implementation compared to other concatenation algorithms,such as BP-OSD,BP-BMA,etc.The simulation results show that the proposed concatenation algorithm is effective,and can achieve a good tradeoff between computational complexity and decoding performance.
Low density parity check (LDPC) codes over are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over codes. This paper proposes a novel variation of the belief propagation algorithm for LDPC codes. The new algorithm results in a reduced hardware complexity when imple- mented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over decoder is feasible for short to medium length codes. The additional com- plexity of the decoder is balanced by the superior performance of LDPC codes.
Recently, both polar codes and low-density parity-check (LDPC) codes have been adopted by 3GPP eMBB scenario. Since both codes exist in one system, it is natural to consider the concatenation scheme of them. In this paper, a merged belief propagation (BP) decoding algorithm for the concatenated codes of polar and LDPC codes is proposed. By jointing factor graphs, this merged algorithm is designed by serially executing the LDPC and polar decoding. According to numerical results, the bit error rate (BER) of this proposed algorithm can achieve a notable improvement for different code rates compared with the conventional separated approach. For (1024, 512) polar code, the performance gain of the proposed scheme is at least 0 5 dB even at a low BER of 1 × 10-2. Finally, further refinements of computational complexity and hardware implementation are also provided in this paper.