The reversible circuit synthesis problem can be reduced to permutation group.This allows Schreier-Sims Algorithm for the strong generating set-finding problem to be used to synthesize reversible circuits using the NCT library.Applying novel optimization rules to minimize the number of gates gives better quantum cost than that shown in the literature.Applications on how to integrate any three irreversible Boolean functions on a single 3-bit reversible circuit will be shown.

IOSR Journal of Computer EngineeringJan 1, 20138 citations

Efficient Algorithms for Optimal 4-Bit Reversible Logic System Synthesis

Zhiqiang Li, Hanwu Chen, Guowu Yang +1 more

Journal of Applied MathematicsJan 1, 20135 citations

Asia and South Pacific Design Automation Conference (ASP-DAC)

A cycle-based synthesis algorithm for reversible logic

Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani

Published Jan 19, 2009• 17 citations

Publisher

Abstract

DOI: 10.5555/1509633.1509801

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Asia and South Pacific Design Automation Conference (ASP-DAC)Jan 1, 200913 citations

Reversible circuit synthesis using a cycle-based approach

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsOct 30, 2006379 citations

An Algorithm for Reversible Logic Circuit Synthesis Based on Tensor Decomposition

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An algorithm for reversible logic synthesis is proposed. The task is, for a given n -bit substitution map, to find a sequence of reversible logic gates that implements the map. The gate library adopted in this work consists of multiple-controlled Toffoli gates with m control bits, where $m \in \lbrace 0, \ldots , n-1\rbrace$ . Controlled gates with large m (> 2) are then further decomposed into smaller gates ( $m \le 2$ ). A primary goal in designing the algorithm is to reduce the number of Toffoli gates, which is known to be universal. The main idea is to view an n -bit substitution map as a rank-2 n tensor and to transform it such that the resulting map can be written as a tensor product of a rank-(2 n -2) tensor and the 2× 2 identity matrix. It can then be seen that the transformed map acts nontrivially on n -1 bits only, meaning that the map to be synthesized becomes ( n -1)-bit substitution. This size reduction process is iteratively applied until it reaches a tensor product of only 2× 2 matrices. The time complexity of the algorithm is exponential in n , as most previously known heuristic algorithms for reversible logic synthesis are, but it terminates within reasonable time for not too large n , which may find practical uses. As stated earlier, our primary target is to reduce the number of Toffoli gates in the output circuit. Benchmark results show that the algorithm works well for hard benchmark functions, but it does not seem advantageous when the function is structured. As an application, the algorithm is applied to find reversible circuits for cryptographic substitution boxes, which are often required in quantum cryptanalysis.An algorithm for reversible logic synthesis is proposed. The task is, for a given n -bit substitution map, to find a sequence of reversible logic gates that implements the map. The gate library adopted in this work consists of multiple-controlled Toffoli gates with m control bits, where $m \in \lbrace 0, \ldots , n-1\rbrace$ . Controlled gates with large m (> 2) are then further decomposed into smaller gates ( $m \le 2$ ). A primary goal in designing the algorithm is to reduce the number of Toffoli gates, which is known to be universal. The main idea is to view an n -bit substitution map as a rank-2 n tensor and to transform it such that the resulting map can be written as a tensor product of a rank-(2 n -2) tensor and the 2× 2 identity matrix. It can then be seen that the transformed map acts nontrivially on n -1 bits only, meaning that the map to be synthesized becomes ( n -1)-bit substitution. This size reduction process is iteratively applied until it reaches a tensor product of only 2× 2 matrices. The time complexity of the algorithm is exponential in n , as most previously known heuristic algorithms for reversible logic synthesis are, but it terminates within reasonable time for not too large n , which may find practical uses. As stated earlier, our primary target is to reduce the number of Toffoli gates in the output circuit. Benchmark results show that the algorithm works well for hard benchmark functions, but it does not seem advantageous when the function is structured. As an application, the algorithm is applied to find reversible circuits for cryptographic substitution boxes, which are often required in quantum cryptanalysis.

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Journal of Applied MathematicsJan 1, 20135 citations

m \in \lbrace 0, \ldots , n-1\rbrace

. Controlled gates with large m (> 2) are then further decomposed into smaller gates (

m \le 2

). A primary goal in designing the algorithm is to reduce the number of Toffoli gates, which is known to be universal. The main idea is to view an n -bit substitution map as a rank-2 n tensor and to transform it such that the resulting map can be written as a tensor product of a rank-(2 n -2) tensor and the 2× 2 identity matrix. It can then be seen that the transformed map acts nontrivially on n -1 bits only, meaning that the map to be synthesized becomes ( n -1)-bit substitution. This size reduction process is iteratively applied until it reaches a tensor product of only 2× 2 matrices. The time complexity of the algorithm is exponential in n , as most previously known heuristic algorithms for reversible logic synthesis are, but it terminates within reasonable time for not too large n , which may find practical uses. As stated earlier, our primary target is to reduce the number of Toffoli gates in the output circuit. Benchmark results show that the algorithm works well for hard benchmark functions, but it does not seem advantageous when the function is structured. As an application, the algorithm is applied to find reversible circuits for cryptographic substitution boxes, which are often required in quantum cryptanalysis.