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International Conference on Natural Computation (ICNC)

Reversible Logic Synthesis of Networks of Positive/Negative Control Gates

Wenying Zhu, Zhijin Guan, Yueqing Hang

Published Jan 1, 2009• 2 citations
Publisher

Abstract

The research in reversible logic has been attracted in recent years. It has applications in quantum computing, low-power CMOS design and nanotechnology. Many methods on how to cascade a reversible network have been proposed. And all these networks are composed of Toffoli/Fredkin gates. In this paper, we present a method that synthesizes a network with family of Positive/Negative Control (PNC) gates. Through introducing some examples for 3×3 reversible functions, and comparing with the network which is composed of Toffoli gates, the results show that introducing the PNC gates can produce an improvement for the number of gates in the reversible network, and have an advantage in reducing the cost of network.

DOI
10.1109/icnc.2009.186

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The research in reversible logic has been attracted in recent years. It has applications in quantum computing, low-power CMOS design and nanotechnology. Many methods on how to cascade a reversible network have been proposed. And all these networks are composed of Toffoli/Fredkin gates. In this paper, we present a method that synthesizes a network with family of Positive/Negative Control (PNC) gates. Through introducing some examples for 3×3 reversible functions, and comparing with the network which is composed of Toffoli gates, the results show that introducing the PNC gates can produce an improvement for the number of gates in the reversible network, and have an advantage in reducing the cost of network.
【Abstract】This paper presents a cascaded algorithm based on reversible network of Positive/Negative Control(PNC) gate, designs the corresponding templates for 3 bit input/output function, and gives a reduction algorithm for the cascaded network. Experimental results show that comparing with the network which is composed of cascaded Toffoli gates, the reversible network using PNC gates contains fewer gates and has an advantage in reducing the cost of network. 【Key words】reversible logic function; Positive/Negative Control(PNC) gate; reversible network; template
Reversible logic has applications in quantum computing, low power CMOS, nanotechnology, optical computing, and DNA computing. The most common reversible gates are the Toffoli gate and the Fredkin gate. Our synthesis algorithm first finds a cascade of Toffoli and Fredkin gates with no backtracking and minimal look-ahead. Next we apply transformations that reduce the size of the circuit. Transformations are accomplished via template matching. The basis for a template is a network with m gates that realizes the identity function. If a sequence in the network to be synthesized matches more than half of a template, then a transformation that reduces the gate count can be applied. In this paper we show that Toffoli and Fredkin gates behave in a similar manner. Therefore, some gates in the templates may not need to be specified-they can match a Toffoli or a Fredkin gate. We formalize this by introducing the box gate. All templates with less than six gates are enumerated and classified. We synthesize all three input, three output reversible functions and compare our results to those obtained previously.
A reversible logic function maps each of the 2m input patterns to a unique output pattern. The network cascade structure problem is to realize a reversible function by a cascade of primitive reversible gates. We present a method that synthesizes a network with family of Toffoli gates. The cascade algorithm finds cascade of Toffoli gates with no backtracking and minimal look-ahead, and apply transformations that reduce the number of gates in the network. We have synthesized all three input and output reversible functions and compare our results to the other optimal results. We also present the results of applying our synthesis method to obtain networks for number of benchmark function.
To further simplify the reversible circuit cascaded by positive/negative control (PNC) gates, new merging, moving and splitting rules of PNC gates were proposed in the paper, and these rules have been proved correct by way of logic algebra. We gave a novel simplification algorithm for reversible logic network of PNC gates by utilizing these rules. Experimental results on all 3-bit reversible functions show that our simplification algorithm is effective, it can decrease the gate count as well as the number of control bits compared to some known results, which were yielded by two excellent heuristic methods. Because the proposed rules have the generality, our simplification algorithm can be easily extended to reversible functions with more number of input bits.
With increase in emphasis on low-power design and quantum computation, research in reversible logic synthesis has gained great attention. Various methods of synthesis exist in the literature, like exact synthesis, heuristic approaches, methods based on group theory, and those based on higher level representation of functions like Binary Decision Diagram (BDD). In this paper a group theory based synthesis approach for reversible circuits is presented, using both positive-control and negative-control Toffoli gates. The method uses group theoretic rules for factoring permutation cycles for synthesis. The use of both positive and negative control Toffoli gates results in reduction of total number of gates required as compared to previous methods based on group theory. Several worked out examples illustrate the advantage of the proposed approach.
Reversible logic finds many applications, especially in the area of quantum computing. A completely specified n-input, n-output Boolean function is called reversible if it maps each input assignment to a unique output assignment and vice versa. Logic synthesis for reversible functions differs substantially from traditional logic synthesis and is currently an active area of research. The authors present an algorithm and tool for the synthesis of reversible functions. The algorithm uses the positive-polarity Reed-Muller expansion of a reversible function to synthesize the function as a network of Toffoli gates. At each stage, candidate factors, which represent subexpressions common between the Reed-Muller expansions of multiple outputs, are explored in the order of their attractiveness. The algorithm utilizes a priority-based search tree, and heuristics are used to rapidly prune the search space. The synthesis algorithm currently targets the generalized n-bit Toffoli gate library. However, other algorithms exist that can convert an n-bit Toffoli gate into a cascade of smaller Toffoli gates. Experimental results indicate that the authors' algorithm quickly synthesizes circuits when tested on the set of all reversible functions of three variables. Furthermore, it is able to quickly synthesize all four-variable and most five-variable reversible functions that were in the test suite. The authors also present results for some benchmark functions widely discussed in literature and some new benchmarks that the authors have developed. The algorithm is shown to synthesize many, but not all, randomly generated reversible functions of as many as 16 variables with a maximum gate count of 25