Fault tolerance plays a major role in quantum computer design. As the quantum environment is not stable enough when the information is read from it, better design techniques with error correcting capability are needed to overcome the information loss due to decoherence in quantum circuits. This paper presents a fault tolerant reversible gate that can be used in quantum computing systems.
Fault tolerance plays a major role in quantum computer design. As the quantum environment is not stable enough when the information is read from it, better design techniques with error correcting capability are needed to overcome the information loss due to decoherence in quantum circuits. This paper presents a fault tolerant reversible gate that can be used in quantum computing systems.
This thesis is concerned with certain theoretical problems that arise naturally in the context of fault-tolerant quantum computation. Fault-tolerance can be defined as the art of building reliable devices from unreliable components, and is of particular importance for quantum computers that aim to precisely control the dynamics of extremely sensitive quantum systems. A model of quantum computation is a specification of the basic building blocks by which a quantum computation is implemented. The best known model is the quantum circuit model, where computations are implemented by means of unitary quantum gates that are applied to two-level quantum systems known as qubits. In a physical implementation of a quantum circuit, the gates and qubits will inevitably be affected by noise. Fault-tolerant quantum circuits are designed to be resilient against the effects of this noise, provided that it is not too strong. Fault-tolerance in the quantum circuit model is well developed thanks to the theory of quantum error-correcting codes. These codes allow for the correction of small numbers of errors introduced by a variety of noise processes. In a fault-tolerant quantum circuit, qubits are replaced with encoded qubits, and quantum gates with encoded gates that are immediately followed by special quantum circuits for error correction. Provided the rate at which errors occur is below a constant threshold value, the accumulation of errors can be checked so that the correct output of the computation correctly determined. The threshold acts as both a measure of how good the design of a quantum circuit is, and also as a target for experimenters aiming to implement quantum circuits. Much current research in quantum computation is aimed at designing quantum circuits that increase the noise threshold, hopefully to the point where it becomes within the reach of experimenters. A fault-tolerant encoded quantum gate must limit the propagation of errors so that the code’s corrective capabilities are not overwhelmed. It is not so easy to design encoded gates that satisfy this property, and to date only a finite handful of such gates are known. In a faulttolerant quantum circuit, all quantum gates must be decomposed or compiled in terms of those that may be implemented fault-tolerantly. In the first part of this thesis, we present two results that may be applied to this problem of gate compilation. The first is a generic method based on the Solovay-Kitaev theorem that may be applied to all quantum gates, but is most effective for those that act on single qubits. We present the Solovay-Kitaev theorem in its simples known form as an algorithm, together with novel constructions that can be used to implement it. Following this we give a two specialized methods for two-qubit gate decomposition, based on the Cartan decomposition of the Lie group SU(4). The cluster-state model of computation is an alternative to the quantum circuit model, and makes use of quantum measurements and highly entangled cluster-states to implement a quantum computation. The fault-tolerant techniques developed for quantum circuits are not immediately applicable in this model, so in order for it to be a realistic candidate for performing computations we prove that such techniques are possible. In the second part of the thesis we prove that constant fault-tolerance thresholds may be achieved in the cluster-state model, and in particular in an adaption to an optical implementation. Following this we design a complete error correction scheme for optical cluster-state computation, and numerically determine the threshold of this model in the face of the dominant noise models likely to affect such an implementation.
In recent years reversible logic has offered a promising alternative to traditional logic circuits. Reversible logic introduces a mechanism which allows theoretically zero energy \ndissipation by eliminating the possibility of information loss. However, it is also desirable \nthat all computation should ideally be done in a fault tolerant manner. To address this we \npropose techniques to achieve fault tolerance in reversible logic based on a passive hardware redundancy technique. We propose two new designs for a reversible majority voter circuit that can be used to implement fault masking. Comparisons to existing designs are presented in terms of cost metrics such as gate count, garbage outputs, constant inputs, and quantum cost. Comparative failure probability analysis of the proposed voter circuits is also provided. Simulation results of the voter circuit failure probabilities over different numbers of trials are also presented. Our approach can be used to determine the circuit failure probability by using the gate failure probabilities. The proposed methodology can provide useful information for future reversible gate fabrication and designing future fault tolerant reversible circuits.
Reversible logic circuits have received emerging attentions in recent years. Reversible logic is widely applied in some new technical fields, such as quantum computing, nanocomputing and optical computing and so on. In this paper, three fault tolerant gates are proposed, ZPL gate, ZQC gate and ZC gate. By using the proposed gates, fault tolerant quantum and reversible BCD adder and skip carry BCD adder are designed, which overcome the limitations of the existing methods. The proposed reversible BCD adders have also parity-preserving property. They are better than the existing counterparts, especially in the quantum cost. Proposed designs have been compared with existing designs with respect to the number of gates, number of garbage outputs and quantum cost.
Quantum technology is a new field of physics and engineering. In emerging areas like Quantum Cryptography, Quantum Computing etc, Quantum circuits play a key role. Quantum circuit is a model for Quantum computation, the computation process of Quantum gates are based on reversible logic. Encoder and Decoder are designed using Quantum gates, and synthesized in the QCAD simulator. Quantum error correction (QEC) is essential to protect quantum information from errors due to quantum noise and decoherence. It is also use to achieve fault-tolerant quantum computation that deals with noise on stored information, faulty quantum gates and faulty measurements.
Quantumcomputation is the modern version of Schrödinger’s cat experiment. It is backed up in principle by the theory and thinking about it can make people equally uncomfortable and excited. Besides, its practical realization seems so extremely challenging that some people even doubt it is possible. On the other hand, we are nowadays much closer to realizing quantum computation and in addition, it has much more implications than Schrödinger’s original cat experiment. One of the major difficulties in realizing quantum computation is the inevitable presence of noise in realistic quantum devices which makes the direct realization of quantum computers impossible. In order to protect quantum information and quantum processes against noise, quantum error correction and fault-tolerance have been devised. Although the gap between experiments and the requirements of fault-tolerance is still daunting, the field of quantum error correction and fault-tolerance extends and influences architectural decisions from the hardware to the ideal quantum programs that we want to run. That is why it has the potential to make or break the practicality of quantum computation and a lot of research effort goes into this field. In this thesis we investigate and improve several aspects of fault-tolerant schemes and quantum error correction. We implement an experiment which validates on a small device the usefulness of fault-tolerance for quantum computation. We investigate the advantages of harnessing quantum continuous degrees of freedom present in the lab to protect discrete quantum information in a scalable way. We establish a framework to analyze the fault-tolerant properties of code deformation techniques which are versatile techniques to process quantum information protected by an error correcting code. We also present some novel code deformation techniques with the potential to increase reliability. Finally we define a new class of quantum error correcting codes, quantum pin codes, with built in capabilities for fault-tolerant quantum gates. We give some practical constructions and show some protocols with interesting parameters. The roads towards universal and fault-tolerant quantum computation are still steep but research efforts are pushing in the right directions.
Quantum computing is a field that shows tremendous possibilities and promise. It can provide an exponential speedup compared to classical computers in many computational problems, including simulations of general quantum mechanical systems, pattern finding and solving linear systems. Quantum computations can be performed by making use of qubits and performing operations, called gates, on them. A physical realisation of a qubit will be faulty, and to combat the errors that will inadvertently but unavoidably occur, the use of a quantum error correction code (QECC) is needed. A QECC is able to correct static errors; errors that occur on the states. However, it can not correct errors that occur on and during the operations. To make the computer resilient to these errors, the implementation of the QECC has to be performed fault-tolerantly. A fault-tolerant implementation of a quantum operation is designed in such a way that errors that happen during the operation, through faulty gates, do not propagate to errors on the states that are not correctable any more by the QECC. Hence, error propagation is a key concept in fault-tolerance. Every element of a general quantum circuit needs to be designed fault-tolerant. One of the elements that will be needed in any realistic quantum computer architecture is the possibility of exchanging the states of two qubits, so that an arbitrary pair of qubits can be brought physically close, allowing the implementation of multi-qubit gates. Exchanging the states of two qubits can be performed by a fault-tolerant SWAP gate, that makes use of one ancilla qubit. In this thesis, a fault-tolerant SWAP operation is implemented on the IBM 5-qubit ‘Tenerife’ device. It is characterized as a quantum channel by performing quantum process tomography (QPT). The CPTP constraints of quantum channels in the framework of QPT are discussed and a method of obtaining a CPTP estimate of an initial QPT reconstruction is given. The error process of the fault-tolerant SWAP is analysed and subsequently compared to a normal implementation of the SWAP gate, on which tomography is performed as well. The main measure that is used in the comparison is the ratio r of multi-qubit errors (or correlated) to single-qubit (or uncorrelated) errors in the two implementations. SPAM errors are an important source of estimated infidelity. To filter these SPAM errors and obtain a better estimate of only the circuits, SPAM errors are approximated to be only measurement errors. The errors are characterized by performing tomography on an arbitrary short identity channel, and subsequently using this as an estimate of the measurement error map. This gives a method to estimate a representation of the circuit itself. We can report on an error ratio r of 0.170±0.0029 for the fault-tolerant SWAP operation and an error ratio r of 1.256 ± 0.0129 for the non-fault-tolerant SWAP operation. However, the total error in the fault-tolerant SWAP is much higher, resulting in a process fidelity Fp = 0.608 for the fault-tolerant implementation and Fp = 0.742 for the normal implementation. This is due to the larger number of gates in the fault-tolerant circuit. This research shows that a SWAP operation can be implemented fault-tolerantly, but that the error rates of the devices need to be reduced before their use becomes viable.