Prior to early this century, the semiconductor microprocessor can be scaled according to the Moore's law, basically doubling its performance in every 18 months. Only recently, the energy efficiency of semiconductor integrated circuits has become a concern than their computational capabilities since their power dissipation scales nonlinear with clock frequency. The specific energy dissipation per logic operation for a modern semiconductor computer is still over 6 orders of magnitude above the thermodynamic threshold kBTln2. It has been known for a long time that this thermodynamic limit on the energy dissipation per logic operation can be overcome by physically and logically reversible circuits. Reversible circuits based on nSQUIDs (negative SQUIDs) or dc SQUIDs (superconducting quantum interference device) with negative mutual inductance between the arms of the SQUID loop, are introduced and investigated in this thesis. First test reversible circuit contains one 8-stage shift register, cells that transfer the input data to the outputs. Dynamic of this circuit illustrates unique properties which agree well with theoretical analysis. Based on the knowledge from the study of shift register, a new timing belt clocking scheme built upon the moving vortices along long Josephson junction (LJJ) is introduced and analyzed. The test circuits for this new scheme contain two 8-stage shift registers, one with direct and the other with inverted outputs. The energy dissipation per nSQUID gate per bit measured for these test circuits at 4 K temperature is already below the thermodynamic threshold. A family of logical gates based on the new timing belt and nSQUIDs shift register are continued to be developed and these gates are capable of fundamentally low energy dissipation and the ability to operate in both irreversible and reversible modes. Moreover, the extremely low energy dissipation in these circuits makes them a natural candidate to support circuitry working in quantum mode with unique advantages.
Prior to early this century, the semiconductor microprocessor can be scaled according to the Moore's law, basically doubling its performance in every 18 months. Only recently, the energy efficiency of semiconductor integrated circuits has become a concern than their computational capabilities since their power dissipation scales nonlinear with clock frequency. The specific energy dissipation per logic operation for a modern semiconductor computer is still over 6 orders of magnitude above the thermodynamic threshold kBTln2. It has been known for a long time that this thermodynamic limit on the energy dissipation per logic operation can be overcome by physically and logically reversible circuits. Reversible circuits based on nSQUIDs (negative SQUIDs) or dc SQUIDs (superconducting quantum interference device) with negative mutual inductance between the arms of the SQUID loop, are introduced and investigated in this thesis. First test reversible circuit contains one 8-stage shift register, cells that transfer the input data to the outputs. Dynamic of this circuit illustrates unique properties which agree well with theoretical analysis. Based on the knowledge from the study of shift register, a new timing belt clocking scheme built upon the moving vortices along long Josephson junction (LJJ) is introduced and analyzed. The test circuits for this new scheme contain two 8-stage shift registers, one with direct and the other with inverted outputs. The energy dissipation per nSQUID gate per bit measured for these test circuits at 4 K temperature is already below the thermodynamic threshold. A family of logical gates based on the new timing belt and nSQUIDs shift register are continued to be developed and these gates are capable of fundamentally low energy dissipation and the ability to operate in both irreversible and reversible modes. Moreover, the extremely low energy dissipation in these circuits makes them a natural candidate to support circuitry working in quantum mode with unique advantages.
We continue to develop a new Superconductor Flux Logic (SFL) family based on nSQUID gates with fundamentally low energy dissipation and the ability to operate in irreversible and reversible modes. Prospective computers utilizing the new gates can keep conventional logically irreversible architectures. In this case the energy dissipation is limited by fundamental thermodynamic laws and could be as low as a fewkBTs per logic operation. Highly exotic and less practical logically and physically reversible circuit architectures are more attractive for us because they enable a reduction of the specific energy dissipation well below the thermodynamic thresholdkBTln2. The reversible option is of interest to us because we can then experimentally demonstrate that all technical mechanisms of the energy dissipation could be cut below the fundamental thermodynamic limit. In other words, we like to set the energy dissipation record for all conventional digital technologies that (if measured inkBT) is about one million times below the best figures achieved in commercially available semiconductor circuits. Besides, we believe that diving below the thermodynamic threshold would have impressive scientific and philosophical impacts. In the paper we introduce a new timing belt clocking scheme and present new circuits. While we still work with test circuits, some of them contain two 8-stage shift registers, one with direct and the other with inverted outputs. The energy dissipation per nSQUID gate per bit measured at 4 K temperature is already below the thermodynamic threshold. We are confident that we passed through the critical phase of the project and we simply need more time to make more sophisticated circuits. The extremely low energy dissipation converts our circuits into a natural candidate to support circuitry for any sensors operating at milli-Kelvin temperatures.
It has been known for a long time that the thermodynamic limit k/sub B/Tln2 on the energy dissipation per logic operation can be overcome by physically and logically reversible circuits. However, explicit experimental demonstration of this is still lacking, and would be highly desirable both in its own right and in view of strong interest in inherently reversible quantum computation. In this work, we suggest a new gate, "negative-inductance SQUID", that is suitable for the experimental demonstration of reversible information processing in Josephson-junction circuits, and present results of its theoretical analysis. We also describe layout-level designs of an individual nSQUID and an 8-cell circular shift register made of nSQUIDs.
One of the most important features of the quantum computing circuits that distinguishes them from the traditional computational models is their full, physical and logical, reversibility at all stages of the calculations. This makes the large-scale architecture of potential quantum and classical reversible computers quite similar. The goal of this work is to analyze this similarity in the case of reversible superconducting logic circuits based on the recently suggested elementary gate, the nSQUID. Specifically, we present the results of numerical simulations and some limited measurements of a reversible 8-bit circular shift register fabricated at HYPRES, Inc., and working in the classical mode. The measured energy dissipation per bit operation per nSQUID is still about 20 times higher than the thermodynamic reversibility threshold of kBTIn 2 at T ap 4 K. We also discuss qualitatively operation of the reversible circuits of galvan- ically-coupled nSQUIDs in the quantum mode which provides the basis for implementation of "flying" superconducting qubits. Such qubits have several attractive features for Josephson-junction quantum logic devices beyond the single- or two-qubit circuits.
Today's industrial digital logic gates are reaching a technological limit and meanwhile, superconducting circuits produce fundamentally different technologies for the future of digital computing. The standard logic is irreversible and yet superconducting circuits allow digital reversible logic with a much higher energy efficiency per gate operation. Previous reversible gate circuits were “adiabatic,” meaning that they used adiabatic-clocking waveforms for their operation power. However, we are studying logic starting from a ballistic model, where ftuxons enable gates using only energy from their inertia. Our ftuxons are defined in Long Josephson Junctions (LJJs) and may travel ballistically, similar to a particle with negligible damping. Once a ftuxon's energy approaches close enough to the gate, a resonance is induced at the gate and the ftuxon loses its definite topology. Gates are comprised of the (few Josephson-penetration-depth long) ends of LJJs and a connecting circuit interface. Only after the resonance does a ftuxon get formed and yield the gate result without external power: a ftuxon for bit-state 0 or an antiftuxon for bit-state 1. Through earlier analysis of the numerically discovered phenomena we find that dynamics can be described with ftuxon- and antiftuxon-like excitations at the ends of LJJs within the gate. The bit-switching action in our gates is resonant indicating fundamentally different dynamics than the classic model of adiabatic reversible circuits. Our ballistic Reversible Fluxon Logic (RFL) gates have no added damping and calculated energy efficiencies of over 97%. Thus in our dynamical process the “bit energy” is preserved. However, irreversible logic completely dissipates this at each operation (e.g., charging energy in CMOS or SFQ energy in irreversible SFQ logic). An RFL gate can achieve a fast gate operation since its resonance is only few JJ plasma periods. We also describe the CNOT in our technology. It is enabled by a couple of vital gates: A IDSN logic gate, similar to our other ballistic gates, and a Store-aNd-Launch (SNL) timing gate to ensure proper synchronization of the bits. The latter allows bit storage followed by launching of a data ftuxon using an adiabatic pulse from a clock ftuxon with lower energy than the data ftuxon for good CNOT efficiency.
Complementary metal-oxide-semiconductor (CMOS) circuit technology has sustainedthe exponential growth of computing power for more than 20 years. However, it hasbeen estimated that the power consumption of a next-generation supercomputer willexceed the power supplied from a single power plant. This indicates the need to dramaticallyimprove the energy efficiency of logic devices to achieve future high-endcomputers.As an extremely energy-efficient logic, we proposed and have been investigatingadiabatic quantum-flux-parametron (AQFP) devices. Due to adiabatic switching operations,its bit energy (energy dissipation per bit) can go below Ic 0, where Ic is acritical current of a Josephson junction and 0 is a single-flux-quantum (SFQ). Ic 0corresponds to the energy dissipated at every 2 phase transition in conventional nonadiabaticsuperconductor logics.We have two objectives in this study. One is to reveal physical energy bounds oncomputation through investigation of the energy efficiency of AQFP logic. The otheris to develop fundamental circuits necessary for energy-efficient computing systemsusing AQFP logic.First, we numerically and experimentally demonstrated the sub-Ic 0 bit-energyoperations of AQFP gates to show that AQFP gates operate in adiabatic modes. Weinvestigated the dependence of energy dissipation and operation margins on circuitparameters. After optimizing the parameters, we calculated the bit energy and the biterror rate at 4.2 K to verify the sub-Ic 0 bit-energy operations at a finite temperature.Additionally, we measured the bit energy of an AQFP gate using a superconductorresonator-based method.Secondly, we numerically demonstrated the sub-kBT bit-energy operations, wherekB is the Boltzmann constant and T is temperature, to show that AQFP gates can operatebeyond thermodynamic energy bounds. We investigated the dependence of energydissipation on operation frequencies and damping conditions of Josephson junctions.By using underdamped junctions, we confirmed the sub-kBT bit-energy operationsat a finite temperature thorough circuit simulation. This result indicates that thereis no minimum energy dissipation required for the operations of AQFP gates unlessthe entropy of the system decreases, which corresponds to the Landauer’s argument on the minimum energy dissipation for computation. Also, we discussed quantummechanicalenergy bounds and experimentally demonstrated AQFP gates with underdampedjunctions.Additionally, we investigated reversible computing using AQFP logic with underdampedjunctions, in order to deal with an important but unresolved question: “Isreversible computing achievable by using practical devices?” We built a purely reversiblegate by using AQFP gates, which we designated as the reversible quantumflux-parametron (RQFP) gate. We calculated its energy dissipation and confirmed thatthere is no minimum energy dissipation for reversible logic operations using RQFPgates. To the best of our knowledge, these are the first calculation results that show nominimum energy dissipation in reversible computing that use practical circuit structures.Moreover, our experimental results have demonstrated the logical and physicalreversibility of the RQFP gate. We believe that this is the first demonstration thatshows both logical and physical reversibility using practical devices.Finally, we proposed a novel energy-efficient latch for AQFP logic, which we designatedas the quantum-flux-latch (QFL). Latches are necessary circuitries in largecomputing systems but had been missing in AQFP logic. We discussed its energyefficiency through simulation and experimentally demonstrated correct operations ofthe QFL and a 1-bit shift register using QFLs. Also, we proposed high-speed test circuitsusing QFLs and experimentally demonstrated logic operations of AQFP circuitsat high speed.We strongly believe that our results showed the extremely high energy efficiency ofAQFP logic. These results will move the AQFP logic to practical usage as extremelyenergy-efficient integrated circuits.
Compared to irreversible gate operations, reversible digital logic gates can provide a fundamental advantage in energy efficiency. Here we discuss previously discovered 1-bit ballistic reversible logic gates and new experimental plans to measure it. The gates consist of long Josephson junctions (LJJs) connected by a circuit interface. The gate dynamics evanescently extends into the LJJs to realize the physically resonant gate operation. It differs from known adiabatic superconducting gates because it does not work in the adiabatic limit. Depending on the gate type, that is the Identity or NOT gate, the polarity of the outgoing fluxon should be preserved or inverted, respectively. The dynamics of the scattering process, originally discovered in full numerical simulation, is understood using collective coordinate analysis. We plan to experimentally study how well a fluxon can travel ballistically towards the interface, and scatter with the designed gate operation. Here we present gate and SQUID-sensing layout designs for a NOT gate. The LJJ circuit layout uses niobium trilayer short junctions with connecting wiring for inductors. Part of the design includes the shunting capacitors at the gate interface which is key for the resonant dynamics in the gates.