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IEEE Transactions on Applied Superconductivity

Delay insensitive RSFQ circuits with zero static power dissipation

Stanislav V. Polonsky

Published Jun 1, 1999• 34 citations
Publisher

Abstract

Total power dissipation in RSFQ circuits consists of two parts, dynamic and static. Dynamic power is dissipated in Josephson junctions performing useful logical and data transmission operations. This dissipation is fundamental and proportional to the data rate (at 4 K, of the order of 10/sup -18/ Joule per bit). Static power is dissipated in resistors used by RSFQ circuits to distribute dc bias current between Josephson junctions. This part of dissipation is not intrinsic to RSFQ circuits and in principle can be eliminated. The goal of this work is to show that Delay Insensitive (DI) RSFQ primitives can be modified so that resistors are no longer required in the dc power supply distribution network, so that the on-chip static power dissipation is absent. In this report we present the schematics for such primitives, define the class of circuits that allow resistor-free current distribution network, and formulate the requirements to the design of this network.

DOI
10.1109/77.783793

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Total power dissipation in RSFQ circuits consists of two parts, dynamic and static. Dynamic power is dissipated in Josephson junctions performing useful logical and data transmission operations. This dissipation is fundamental and proportional to the data rate (at 4 K, of the order of 10/sup -18/ Joule per bit). Static power is dissipated in resistors used by RSFQ circuits to distribute dc bias current between Josephson junctions. This part of dissipation is not intrinsic to RSFQ circuits and in principle can be eliminated. The goal of this work is to show that Delay Insensitive (DI) RSFQ primitives can be modified so that resistors are no longer required in the dc power supply distribution network, so that the on-chip static power dissipation is absent. In this report we present the schematics for such primitives, define the class of circuits that allow resistor-free current distribution network, and formulate the requirements to the design of this network.
Abstract Energy-efficient rapid single flux quantum (ERSFQ) circuits suppress the dominant static power dissipation of Rapid SFQ logic by replacing bias resistors with current-limiting bias Josephson junctions (JJs) and inductors. In practice, however, these JJs introduce power dissipation in the DC bias network due to switching events required to correct data-dependent phase imbalances, with dissipation often comparable to that of dynamic power. This paper presents xeSFQ, a new SFQ logic family that integrates alternating SFQ (xSFQ) encoding with ERSFQ biasing. By enforcing a single pulse per line per logical cycle, xeSFQ maintains uniform phase across the circuit, thereby eliminating bias JJ switching during operation and achieving zero bias network power dissipation. Extensive analog simulations and logic synthesis results, from individual gates to ISCAS and EPFL benchmarks, validate this hypothesis and demonstrate the efficiency and scalability advantages of the proposed approach.
We present a novel, resistor-free approach to dc biasing of RSFQ circuits, known as Energy-efficient RSFQ (ERSFQ). This biasing scheme does not dissipate energy in the static (non-active) mode, and dissipates orders of magnitude less power than traditional RSFQ while operating. Using this approach, we have designed, fabricated and successfully tested at low and high speed a D flip-flop with complementary outputs and several static frequency dividers. We present the method, demonstrate experimental results, and discuss future implementations of ERSFQ.
Superconducting single flux quantum (SFQ) circuits have been shown to offer huge advantages that are ideal for high performance computing applications. These circuits can operate at very high frequencies (tens of GHz) but consume very low power (from nanowatts to microwatts per gate). Energy-efficient SFQ (ERSFQ) circuits, evolved from traditional rapid SFQ (RSFQ) circuits, were invented with the goal of elimination of static power dissipation. When compared with RSFQ circuits, ERSFQ circuits require a new biasing network that includes biasing Josephson junction(s), biasing inductor(s), and feeding Josephson transmission line(s). Some general suggestions on how to design the network have been offered, but a detailed analysis and optimization scenario for the network is still to be provided. In this paper, we first optimize the previously reported DC-biased two-Josephson junction per bit RSFQ shift register circuit, which can be used to provide a more robust, energy-efficient, and high memory capacity storage unit. The simulated power dissipation of 16-bit RSFQ shift register is 0.45 μW per bit when operating at 21.7 GHz. We then convert the RSFQ-based shift register into an ERSFQ structure and investigate the effects of the ERSFQ bias network on the margins of the ERSFQ circuit. Finally, we propose a more comprehensive optimization method for the ERSFQ biasing network.
High current requirements in single flux quantum (SFQ) circuits pose scalability challenges, contributing to issues such as high thermal loads, static power dissipation, and increased sensitivity to flux trapping under non-ideal shielding or cool down conditions. AC biasing, successfully used in other superconductive logic families, has been integrated into rapid single flux quantum (RSFQ) circuits and typically includes AC-to-DC converters, introducing area and complexity overhead. This work proposes an alternative method for applying AC biasing to existing RSFQ circuits using inductively coupled bias junctions, eliminating the need for AC-to-DC converters. This approach also combines resistive DC biasing with inductive AC biasing, reducing static power dissipation. The proposed approach targets clock splitters, which are significant contributors to on-chip current demand, achieving an average 94% reduction in splitter current and a 62% reduction in overall system current with a Josephson junction overhead of 6.5%. The technique is compatible with conventional RSFQ system architectures and logic families while significantly enhancing energy efficiency and scalability.
Rapid single flux quantum (RSFQ) electronics is based on the Josephson junction as an active switching element. In standard RSFQ circuits its switching energy is much lower than the static power consumption caused by the resistive current distribution network. Due to this thermal heating of the chip, the maximum number of junctions on a single chip is limited to about 1 million. The frequency-dependent contribution to power dissipation from junction switchings is only about 2 percent of the static one. This fact limits the direct construction of VLSI systems for high-performance computing as well as small-scale circuit applications in the vicinity of ultra-sensitive detectors or even quantum circuits. We present an assessment of different approaches for reducing the static power consumption by investigating the potential of inductive bias distribution networks as well as reduced critical currents. We analyse the operation stability of simple digital circuits with 5 times smaller critical currents at 4.2 K. The combination of the reduced critical currents and inductive biasing can provide digital superconductive circuits with significantly reduced static power consumption.
We have demonstrated rapid-single-flux-quantum (RSFQ) circuits with reduced power consumptions by lowering bias voltages and critical currents. The power consumption including a power consumption of a bias resistor is measured to be around 1 nW/JJ in 8-bit shift registers, while the operating frequency ranges from 7.5 GHz to 20 GHz. we lower bias voltages applied to RSFQ circuits. The values of bias resistances are proportional to bias voltages. At lowered bias voltages, the power consumption of the bias resistor is reduced. When a voltage begins to be generated at a Josephson junction, the net current provided to the junction and to the shunt resistor is decreased. As a result, the magnitude of the voltage is suppressed, and the power consumption of the shunt resistor is reduced. The power energy-delay product is about 70 times smaller and the the energy-delay product is more than 13 times smaller than that of the conventional RSFQ circuits. Low poewer SFQ circuits are superior in terms of energy-delay product to semiconductor circuits though the power consumption of SFQ cicuits contains the refrigerating machine.