Existing synthesis-related cost functions are explored and five fundamental properties of an efficient quantum circuit implementation are introduced. In addition, a thorough set of metrics for quantum circuit synthesis are proposed and applied on some well-known synthesis algorithms. Our analysis reveals the requirement of proposing new synthesis algorithms to produce realizable circuits. A new heuristic is also introduced which improves the results of a commonly used synthesis algorithm in terms of the proposed synthesis-related metrics.
Existing synthesis-related cost functions are explored and five fundamental properties of an efficient quantum circuit implementation are introduced. In addition, a thorough set of metrics for quantum circuit synthesis are proposed and applied on some well-known synthesis algorithms. Our analysis reveals the requirement of proposing new synthesis algorithms to produce realizable circuits. A new heuristic is also introduced which improves the results of a commonly used synthesis algorithm in terms of the proposed synthesis-related metrics.
Many synthesis approaches for reversible and quantum logic have been proposed so far. However, most of them generate circuits with respect to simple metrics, i.e. gate count or quantum cost. On the other hand, to physically realize reversible and quantum hardware, additional constraints exist. In this paper, we describe cost metrics beyond gate count and quantum cost that should be considered while synthesizing reversible and quantum logic for the respective target technologies. We show that the evaluation of a synthesis approach may differ if additional costs are applied. In addition, a new cost metric, namely Nearest Neighbor Cost (NNC) which is imposed by realistic physical quantum architectures, is considered in detail. We discuss how existing synthesis flows can be extended to generate optimal circuits with respect to NNC while still keeping the quantum cost small.
It is important to construct quantum algorithms within shallow-depth quantum circuits due to the current imperfections and decoherence in quantum devices. Efficient quantum circuit synthesis and optimization are critical tasks that generate relatively small quantum circuits tailored to specific requirements. However, an efficient circuit may vary depending on the physical realization platforms of quantum computers. For example, the Clifford+T gate library has recently gained prominence for its superior fault tolerance and error correction capabilities, but the T gate dominates circuit execution time. Therefore, the objectives of synthesis algorithms in this gate set include reducing T-depth and T-count, as well as overall circuit depth and gate count. Most traditional synthesis methods produce a single optimized circuit. In contrast, this study introduces a multi-objective quantum-inspired tabu search algorithm in quantum circuit synthesis to construct a diverse set of optimized circuits based on four distinct metrics. The values of these metrics in the optimized circuit display the entanglement relationship, and the proposed method simulates the formula to assist in building the entangled optimal circuit. Results show that the construction of the Pareto front can flexibly offer a variety of functionally equivalent circuits that adapt to advancements in quantum technology. Providing multiple optimized circuit structures facilitates circuit replacement and further simplification, thereby enhancing the development of quantum computing.
Quantum computing is the basis of a new revolution. Several quantum computers are already available and, with them, quantum programming languages, quantum software development kits and platforms, quantum error correction and optimization tools are proposed and presented continuously. In connection with this, disciplines such as the Quantum Software Engineering are appearing for applying the knowledge acquired through time in their corresponding classical relatives. Besides, measurement is well known as a key factor for assessing, and improving if needed, the quality of any model in terms of, for instance, its understandability. The easier to understand a model is, the easier to maintain, reuse, etc. In this work, we present the definition of a set of metrics for assessing the understandability of quantum circuits. Some examples of the calculation of the metrics are also presented. This is just the beginning of a more thorough process in which they will be empirically validated by the performance of empirical studies, especially experiments.
Quantum circuit synthesis is the process in which an arbitrary unitary operation is decomposed into a sequence of gates from a universal set, typically one which a quantum computer can implement both efficiently and fault-tolerantly. As physical implementations of quantum computers improve, the need is growing for tools that can effectively synthesize components of the circuits and algorithms they will run. Existing algorithms for exact, multi-qubit circuit synthesis scale exponentially in the number of qubits and circuit depth, leaving synthesis intractable for circuits on more than a handful of qubits. Even modest improvements in circuit synthesis procedures may lead to significant advances, pushing forward the boundaries of not only the size of solvable circuit synthesis problems, but also in what can be realized physically as a result of having more efficient circuits. We present a method for quantum circuit synthesis using deterministic walks. Also termed pseudorandom walks, these are walks in which once a starting point is chosen, its path is completely determined. We apply our method to construct a parallel framework for circuit synthesis, and implement one such version performing optimal T -count synthesis over the Clifford+ T gate set. We use our software to present examples where parallelization offers a significant speedup on the runtime, as well as directly confirm that the 4-qubit 1-bit full adder has optimal T -count 7 and T -depth 3.
Reversible logic circuits have been historically motivated by theoretical research in low-power, and recently attracted interest as components of the quantum algorithm, optical computing and nanotechnology. However due to the intrinsic property of reversible logic, traditional irreversible logic design and synthesis methods cannot be carried out. Thus a new set of algorithms are developed correctly to synthesize reversible logic circuit. This paper presents a comprehensive literature review with comparative study on heuristic based reversible logic synthesis. It reviews a range of heuristic based reversible logic synthesis techniques reported by researchers (BDD-based, cycle-based, search-based, non-search-based, rule-based, transformation-based, and ESOP-based). All techniques are described in detail and summarized in a table based on their features, limitation, library used and their consideration metric. Benchmark comparison of gate count and quantum cost are analysed for each synthesis technique. Comparing the synthesis algorithm outputs over the years, it can be observed that different approach has been used for the synthesis of reversible circuit. However, the improvements are not significant. Quantum cost and gate count has improved over the years, but arguments and debates are still on certain issues such as the issue of garbage outputs that remain the same. This paper provides the information of all heuristic based synthesis of reversible logic method proposed over the years. All techniques are explained in detail and thus informative for new reversible logic researchers and bridging the knowledge gap in this area.
Reversible logic circuits have been historically motivated by theoretical research in low-power, and recently attracted interest as components of the quantum algorithm, optical computing and nanotechnology. However due to the intrinsic property of reversible logic, traditional irreversible logic design and synthesis methods cannot be carried out. Thus a new set of algorithms are developed correctly to synthesize reversible logic circuit. This paper presents a comprehensive literature review with comparative study on heuristic based reversible logic synthesis. It reviews a range of heuristic based reversible logic synthesis techniques reported by researchers (BDD-based, cycle-based, search-based, non-search-based, rule-based, transformation-based, and ESOP-based). All techniques are described in detail and summarized in a table based on their features, limitation, library used and their consideration metric. Benchmark comparison of gate count and quantum cost are analysed for each synthesis technique. Comparing the synthesis algorithm outputs over the years, it can be observed that different approach has been used for the synthesis of reversible circuit. However, the improvements are not significant. Quantum cost and gate count has improved over the years, but arguments and debates are still on certain issues such as the issue of garbage outputs that remain the same. This paper provides the information of all heuristic based synthesis of reversible logic method proposed over the years. All techniques are explained in detail and thus informative for new reversible logic researchers and bridging the knowledge gap in this area.