Functional verification is an important design method for verifying functional equivalence between a simplified quantum Boolean circuit and original one. During the design process, checking the equivalence of two quantum Boolean circuits is necessary. In this paper, we present an algorithm that can efficiently and easily verify two quantum Boolean circuits by using the back propagation method. For a set of input vectors, the idea of the algorithm is to find the checking vectors that output vectors are different from input vectors by a backward tracking process.
Functional verification is an important design method for verifying functional equivalence between a simplified quantum Boolean circuit and original one. During the design process, checking the equivalence of two quantum Boolean circuits is necessary. In this paper, we present an algorithm that can efficiently and easily verify two quantum Boolean circuits by using the back propagation method. For a set of input vectors, the idea of the algorithm is to find the checking vectors that output vectors are different from input vectors by a backward tracking process.
Equivalence checking of quantum circuits is an essential element in quantum program compilation, in which a quantum program can be synthesized into different quantum circuits that may vary in the number of qubits, initialization requirements, and output states. Verifying the equivalences among the implementation variants requires proper generality. Although different notions of quantum circuit equivalence have been defined, prior methods cannot check observational equivalence between two quantum circuits whose qubits are partially initialized, which is referred to as partial equivalence. In this work, we prove a necessary and sufficient condition for two circuits to be partially equivalent. Based on the condition, we devise algorithms for checking quantum circuits whose partial equivalence cannot be verified by prior approaches. Experiment results confirm the generality and demonstrate the efficiency and effectiveness of our method. Our result may unleash the optimization power of quantum program compilation to take more aggressive steps.
Boolean matching is an important problem in logic synthesis and verification. Despite being well-studied for conventional Boolean circuits, its treatment for reversible logic circuits remains largely, if not completely, missing. This work provides the first such study. Given two (black-box) reversible logic circuits that are promised to be matchable, we check their equivalences under various input/output negation and permutation conditions subject to the availability/unavailability of their inverse circuits. Notably, among other results, we show that the equivalence up to input negation and permutation is solvable in quantum polynomial time, while its classical complexity is exponential. This result is arguably the first demonstration of quantum exponential speedup in solving design automation problems. Also, as a negative result, we show that the equivalence up to both input and output negations is not solvable in quantum polynomial time unless UNIQUE-SAT is, which is unlikely. This work paves the theoretical foundation of Boolean matching reversible circuits for potential applications, e.g., in quantum circuit synthesis.
Synthesis of quantum circuits is essential for building quantum computers. It is important to verify that the circuits designed perform the correct functions. In this paper, we propose an algorithm which can be used to verify the quantum circuits synthesized by any method. The proposed algorithm is based on BDD (Binary Decision Diagram) and is called X-decomposition Quantum Decision Diagram (XQDD). In this method, quantum operations are modeled using a graphic method and the verification process is based on comparing these graphic diagrams. We also develop an algorithm to verify reversible circuits even if they have a different number of garbage qubits. In most cases, the number of nodes used in XQDD is less than that in other representations. In general, the proposed method is more efficient in terms of space and time and can be used to verify many quantum circuits in polynomial time.
In the not-so-distant future, quantum computing will change the way we tackle certain problems. It promises to dramatically speed-up many chemical, financial, cryptographical, and machine-learning applications. However, in order to capitalize on those promises, complex design flows composed of steps, such as compilation, decomposition, mapping, or transpilation need to be employed before being able to execute a conceptual quantum algorithm on an actual device. This results in many descriptions at various levels of abstraction which may significantly differ from each other. The complexity of the underlying design problems makes it ever more important to not only provide efficient solutions for the single steps but also to verify that the originally intended functionality is preserved throughout all levels of abstraction. This motivates methods for equivalence checking of quantum circuits. However, most existing methods for this are inspired by equivalence checking in the classical realm and have merely been extended to support quantum circuits (i.e., circuits which do not only rely on 0's and 1's but also employ superposition and entanglement). In this work, we propose an advanced methodology that takes the different paradigms of quantum circuits not only as a burden but as an opportunity. In fact, the proposed methodology explicitly utilizes characteristics unique to quantum computing in order to overcome the shortcomings of existing approaches. We show that by exploiting the reversibility of quantum circuits, complexity can be kept feasible in many cases. Moreover, we show that, in contrast to the classical realm, simulation is very powerful in verifying quantum circuits. Experimental evaluations confirm that the resulting methodology allows one to conduct equivalence checking dramatically faster than ever before-in many cases just a single simulation run is sufficient. An implementation of the proposed equivalence checking flow is publicly available at https://iic.jku.at/eda/research/quantum_verification/.
The tabulation method can be used with a computer to simplify Boolean logic functions with up to 6 or more variables, especially with a large number of variables. For the various applications, their circuits usually are complex and we must simplify the circuit design to the best of our ability. In this paper, we present an algorithm that can efficiently simplify a quantum Boolean circuit with an arbitrary number of input variables by using the tabulation method. In terms of the space consumption, we use only one auxiliary qubit as the output qubit, and keep all the input qubits unchanged.
Quantum computing is gaining serious momentum in these days. With increasing capabilities of corresponding devices also comes the need for efficient and automated tools to design them. Verification, i.e., ensuring that the originally intended functionality of a quantum algorithm/circuit is preserved throughout all layers of abstraction during the design process, is a vital part of the quantum software stack. In this work, we present QCEC , a tool for quantum circuit equivalence checking which is part of the JKQ toolset for quantum computing. By exploiting characteristics unique to quantum computing, the tool allows users to efficiently verify the equivalence of two quantum circuits using a variety of methods and strategies.