Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

The Journal of the Institute of Electrical Engineers of Japan

Information-Processing Circuits Using Single Flux Quanta

Akira Fujimaki, Masamitsu Tanaka

Published Jan 1, 2010• 0 citations
Publisher

Abstract

る。すべての論理ゲートにクロック信号を供給し，データ 信号との同期をとる必要があることから，SFQ 論理ゲー トは本質的にラッチ機能を有するという，ユニークな特徴 を持つ。クロック周期はパルス幅の 5 -10 倍あればよ く，100 GHz を超える動作も実証されている (3) 。 近年，マイクロストリップやストリップ構造の導波路を 集積回路内に形成し，配線に用いる受動線路(Passive Transmission Line：PTL)技術が確立された (4) (5) 。これ は，超電導配線の超低損失性を利用し，電圧パルスを電磁 波として弾道的に伝搬させるものである。電圧レベルを信 号とする半導体回路のように配線容量を充放電する必要が ないため，1 本の配線上に複数の SFQ パルスを乗せられ る。チップ内のみならずチップ間でも，信号線当たり 100 Gbps 以上の高スループットの信号伝送が可能であること 1．はじめに 単一磁束量子(Single Flux Quantum：SFQ)回路は， 超電導体リング中の磁束量子を情報担体とし，

DOI
10.1541/ieejjournal.130.159

Related papers

Recent development and perspective of ultra-high-speed microprocessors using single-flux-quantum circuits

吉川, 信行, ヨシカワ, ノブユキ, Yoshikawa, Nobuyuki

超伝導ループ中の量子化磁束を情報担体とする単一磁束量子(SFQ)回路は，動作スピードと消費電力において半導体を凌駕する性能をもつ．近年，SFQ集積回路の設計技術とプロセス技術の進歩により，1万接合を超えるSFQ回路の動作が可能となってきた．本論文では，SFQ回路の動作原理，性能，要素技術について解説するとともに，SFQマイクロプロセッサの最近の研究開発動向を紹介する．更に，ハイエンドコンピュータ応用を中心に本技術の今後の展望を述べる．

•Mar 1, 2008•0 citations

単一磁束量子パルス周波数変調型D/A変換器のGHz信号生成回路への応用

Seiya Hayashi, 島田, 宏, 義直 水柿

単一磁束量子(Single Flux Quantum: SFQ)回路の応用の一つとして交流電圧標準がある．これを実現するために，交流ジョセフソン効果で定義された高精度な電圧を生成するパルス周波数変調型D/A 変換器(Digital/Analog Converter: DAC) の開発が行われている．“sum of Selected Bit Sequences (-SBS)”型と呼ばれるDAC はその一つであり，生成電圧の精度の高さを保ちながら，取り扱うSFQ パルス列周波数が120 GHz 程度に達する高速動作性を有する．本研究では，-SBS DAC の高速動作性を活かしてマイクロ波を生成する回路を設計し，数値計算により動作検証並びに動作可能範囲の探索を行った．結果として，目標であった周波数1 GHz の両極性疑似正弦波に相当するSFQ パルス列の周波数変調を達成した．また，回路の生成できる正弦波の周波数は10 MHz–1 GHz であった．

•Oct 1, 2024•0 citations

A design approach to passive interconnects for single flux quantum logic circuits

Y. Hashimoto, Shinichi Yorozu, Y. Kameda +1 more

We developed a design approach for interface circuits to connect Single Flux Quantum (SFQ) cells by using passive transmission lines (PTL's). In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to previously designed SFQ cells and the standard interface circuit to connect the SFQ cells by using PTL's. The key point is the use of approximately the same interface circuit with every SFQ cell to maintain the matching condition between the interface circuit and the PTL's. Based on this approach, we designed an interface circuit and a test circuit composed of two D-flip-flops connected using 2-mm-long PTL's via the interface circuits. The impedance of the PTL was 2 /spl Omega/. We achieved high-speed operation of the test circuit up to 35 GHz with a bias margin of -15/+30%.

IEEE Transactions on Applied Superconductivity•Jun 1, 2003•53 citations

10kA/cm^2Nb Processを用いたSFQ浮動小数点乗算器の50GHzでの動作評価(信号処理基盤技術及びその応用,一般)

泰浩 島村, 世樹 貝沼, 史滋 宮岡 +5 more

電子情報通信学会技術研究報告. SCE, 超伝導エレクトロニクス•Jul 15, 2010•0 citations

Optimization of Passive Transmission Lines for Single Flux Quantum Circuits

Benjamin Chonigman, Ashish Shukla, Mustapha Habib +6 more

Passive transmission lines (PTLs) provide an energy-efficient means of transporting pulsed single flux quantum (SFQ) signals between logic gates and blocks on a chip, or even between chips through a multi-chip module carrier. Although functional up to 70 GHz, our previous designs manifested sharp, length-dependent resonances resulting in diminished operating margins. These are particularly inconvenient since the resonant length is about 1 mm at 40–50 GHz, where most SFQ circuits currently function. To avoid the need to keep the PTLs < 1 mm in length, we have optimized the PTL driver-receiver pairs to sufficiently suppress these resonances; this helps facilitate the use of automated routing tools. We present experimental results, in the 10-70 GHz frequency range, for different driver-receiver pairs designed for PTLs in our dual RSFQ-ERSFQ cell library. This cell library, targeting MIT Lincoln Laboratory's SFQ5ee fabrication process, uses PTLs with two types of ground plane configuration. The first variant has signal in M1 and/or M3 with symmetrical ground planes in M0, M2 and/or M2, M4 respectively. The second variant has signal in M2 and/or M3 with asymmetrical ground planes in M1 and M4. We also present a comparison with wider, 4 Ω, PTLs that are more suitable for transport between distant logic blocks. Next, we present experimental results of PTL lengths ranging from 1.2-12 mm over the same 10-70 GHz frequency range. Finally, we report on the design of circuits for investigating crosstalk between two PTLs and their measurement results.

IEEE Transactions on Applied Superconductivity•Feb 26, 2021•14 citations

A New Design Methodology for Single-Flux-Quantum (SFQ) Logic Circuits Using Passive-Transmission-Line (PTL) Wiring

Y.. Kameda, Shinichi Yorozu, Y. Hashimoto

The introduction of passive-transmission-line (PTL) wiring to large-scale SFQ logic circuits offers several advantages over traditional Josephson-transmission-line (JTL) wiring, such as smaller wiring area, less delay, lower power consumption, and more freedom in routing. PTL wiring can drastically change the style of designing SFQ logic circuits. We propose a new methodology for designing large-scale SFQ circuits using PTL wiring. Aiming at generalizing SFQ circuit design, we chose synchronous clocking. We developed a placer that was suitable for SFQ circuit design to assist us with the new design methodology. The placer first synthesizes an H-tree clock distribution network, placing SFQ pulse splitter cells at each branch. It then places logic cells to minimize the maximum length of data PTL wires, aiming at higher operating speeds. Finally, a router completes the PTL wiring. To evaluate the design methodology we designed an 8-bit general purpose RISC processor. Within twelve hours, we obtained a 15-mm-square SFQ circuit that could operate up to 27.6 GHz. We adopted an advanced Nb process, which was characterized by a critical current density of 10 kA/cm2, two 5-mum-wide PTL wiring layers, and a minimum cell size of 30 mum times 30 mum. The circuit consisted of about 20,000 logic cells, which approximated more than 400,000 Josephson junctions including splitters to distribute the clock signal.

IEEE Transactions on Applied Superconductivity•Jun 1, 2007•52 citations
る。すべての論理ゲートにクロック信号を供給し，データ 信号との同期をとる必要があることから，SFQ 論理ゲー トは本質的にラッチ機能を有するという，ユニークな特徴 を持つ。クロック周期はパルス幅の 5 -10 倍あればよ く，100 GHz を超える動作も実証されている (3) 。 近年，マイクロストリップやストリップ構造の導波路を 集積回路内に形成し，配線に用いる受動線路(Passive Transmission Line：PTL)技術が確立された (4) (5) 。これ は，超電導配線の超低損失性を利用し，電圧パルスを電磁 波として弾道的に伝搬させるものである。電圧レベルを信 号とする半導体回路のように配線容量を充放電する必要が ないため，1 本の配線上に複数の SFQ パルスを乗せられ る。チップ内のみならずチップ間でも，信号線当たり 100 Gbps 以上の高スループットの信号伝送が可能であること 1．はじめに 単一磁束量子(Single Flux Quantum：SFQ)回路は， 超電導体リング中の磁束量子を情報担体とし，
超伝導ループ中の量子化磁束を情報担体とする単一磁束量子(SFQ)回路は，動作スピードと消費電力において半導体を凌駕する性能をもつ．近年，SFQ集積回路の設計技術とプロセス技術の進歩により，1万接合を超えるSFQ回路の動作が可能となってきた．本論文では，SFQ回路の動作原理，性能，要素技術について解説するとともに，SFQマイクロプロセッサの最近の研究開発動向を紹介する．更に，ハイエンドコンピュータ応用を中心に本技術の今後の展望を述べる．
単一磁束量子(Single Flux Quantum: SFQ)回路の応用の一つとして交流電圧標準がある．これを実現するために，交流ジョセフソン効果で定義された高精度な電圧を生成するパルス周波数変調型D/A 変換器(Digital/Analog Converter: DAC) の開発が行われている．“sum of Selected Bit Sequences (-SBS)”型と呼ばれるDAC はその一つであり，生成電圧の精度の高さを保ちながら，取り扱うSFQ パルス列周波数が120 GHz 程度に達する高速動作性を有する．本研究では，-SBS DAC の高速動作性を活かしてマイクロ波を生成する回路を設計し，数値計算により動作検証並びに動作可能範囲の探索を行った．結果として，目標であった周波数1 GHz の両極性疑似正弦波に相当するSFQ パルス列の周波数変調を達成した．また，回路の生成できる正弦波の周波数は10 MHz–1 GHz であった．
We developed a design approach for interface circuits to connect Single Flux Quantum (SFQ) cells by using passive transmission lines (PTL's). In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to previously designed SFQ cells and the standard interface circuit to connect the SFQ cells by using PTL's. The key point is the use of approximately the same interface circuit with every SFQ cell to maintain the matching condition between the interface circuit and the PTL's. Based on this approach, we designed an interface circuit and a test circuit composed of two D-flip-flops connected using 2-mm-long PTL's via the interface circuits. The impedance of the PTL was 2 /spl Omega/. We achieved high-speed operation of the test circuit up to 35 GHz with a bias margin of -15/+30%.
Passive transmission lines (PTLs) provide an energy-efficient means of transporting pulsed single flux quantum (SFQ) signals between logic gates and blocks on a chip, or even between chips through a multi-chip module carrier. Although functional up to 70 GHz, our previous designs manifested sharp, length-dependent resonances resulting in diminished operating margins. These are particularly inconvenient since the resonant length is about 1 mm at 40–50 GHz, where most SFQ circuits currently function. To avoid the need to keep the PTLs < 1 mm in length, we have optimized the PTL driver-receiver pairs to sufficiently suppress these resonances; this helps facilitate the use of automated routing tools. We present experimental results, in the 10-70 GHz frequency range, for different driver-receiver pairs designed for PTLs in our dual RSFQ-ERSFQ cell library. This cell library, targeting MIT Lincoln Laboratory's SFQ5ee fabrication process, uses PTLs with two types of ground plane configuration. The first variant has signal in M1 and/or M3 with symmetrical ground planes in M0, M2 and/or M2, M4 respectively. The second variant has signal in M2 and/or M3 with asymmetrical ground planes in M1 and M4. We also present a comparison with wider, 4 Ω, PTLs that are more suitable for transport between distant logic blocks. Next, we present experimental results of PTL lengths ranging from 1.2-12 mm over the same 10-70 GHz frequency range. Finally, we report on the design of circuits for investigating crosstalk between two PTLs and their measurement results.
The introduction of passive-transmission-line (PTL) wiring to large-scale SFQ logic circuits offers several advantages over traditional Josephson-transmission-line (JTL) wiring, such as smaller wiring area, less delay, lower power consumption, and more freedom in routing. PTL wiring can drastically change the style of designing SFQ logic circuits. We propose a new methodology for designing large-scale SFQ circuits using PTL wiring. Aiming at generalizing SFQ circuit design, we chose synchronous clocking. We developed a placer that was suitable for SFQ circuit design to assist us with the new design methodology. The placer first synthesizes an H-tree clock distribution network, placing SFQ pulse splitter cells at each branch. It then places logic cells to minimize the maximum length of data PTL wires, aiming at higher operating speeds. Finally, a router completes the PTL wiring. To evaluate the design methodology we designed an 8-bit general purpose RISC processor. Within twelve hours, we obtained a 15-mm-square SFQ circuit that could operate up to 27.6 GHz. We adopted an advanced Nb process, which was characterized by a critical current density of 10 kA/cm2, two 5-mum-wide PTL wiring layers, and a minimum cell size of 30 mum times 30 mum. The circuit consisted of about 20,000 logic cells, which approximated more than 400,000 Josephson junctions including splitters to distribute the clock signal.