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ACM Symposium on Parallelism in Algorithms and Architectures (SPAA)

Brief announcement

James E. Levy, Anand Ganti, Cynthia A. Phillips, Benjamin Hamlet, Andrew J. Landahl, Thomas M. Gurrieri, Robert D. Carr, Malcolm S. Carroll

Published Aug 11, 2009• 7 citations
Publisher

Abstract

We present and analyze an architecture for a logical qubit memory that is tolerant of faults in the processing of silicon double quantum dot (DQD) qubits. A highlight of our analysis is an in-depth consideration of the constraints faced when integrating DQDs with classical control electronics.
DOI
10.1145/1583991.1584039

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We describe a fault-tolerant memory for an error-corrected logical qubit based on silicon double quantum dot physical qubits. Our design accounts for constraints imposed by supporting classical electronics. A significant consequence of the constraints is to add error-prone idle steps for the physical qubits. Even using a schedule with provably minimum idle time, for our noise model and choice of error-correction code, we find that these additional idles negate any benefits of error correction. Using additional qubit operations, we can greatly suppress idle-induced errors, making error correction beneficial, provided the qubit operations achieve an error rate less than 2×10−52 \times 10^{-5}2×10−5. We discuss other consequences of these constraints such as error-correction code choice and physical qubit operation speed. While our analysis is specific to this memory architecture, the methods we develop are general enough to apply to other architectures as well.
Abstract Even the quantum simulation of an apparently simple molecule such as Fe2S2requires a considerable number of qubits of the order of 106, while more complex molecules such as alanine (C3H7NO2) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore’s law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for fault-tolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal–oxide–semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal–oxide–semiconductor quantum processor to be within 1 and 100 GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metal–oxide–semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal–oxide–semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal–oxide–semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via time-division, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4 Mqb/cm2for the 10 and 7-nm technology nodes, respectively, for the Steane code. The density is one and two orders of magnitude less for surface codes and for concatenated codes, respectively. Such values provide a benchmark for the development of fault-tolerant quantum algorithms by circuital quantum information based on silicon platforms and a guideline for other technologies in general.