We have been developing a large-scale reconfigurable data path (LSRDP) based on single-flux-quantum (SFQ) circuit technology for high-performance computing systems. In the SFQ LSRDP, a large number of SFQ floating-point adders (FPAs) and floating-point multipliers (FPMs) are directly connected to each other through routing networks to reduce a memory access rate. In this paper, we show our recent results about the SFQ FPAs and FPMs. Utilization of the National Institute of Advanced Industrial Science and Technology's 10-kA/cm2Nb process makes it possible to accelerate the clock frequency to more than 50 GHz. We successfully demonstrated the high-speed operation of single- precision FPAs and FPMs, whose clock frequency is beyond 50 GHz, by on-chip high-speed tests. We estimate the performance and energy efficiency of SFQ FPAs and FPMs based on the designed circuits.
We have been developing a large-scale reconfigurable data path (LSRDP) based on single-flux-quantum (SFQ) circuit technology for high-performance computing systems. In the SFQ LSRDP, a large number of SFQ floating-point adders (FPAs) and floating-point multipliers (FPMs) are directly connected to each other through routing networks to reduce a memory access rate. In this paper, we show our recent results about the SFQ FPAs and FPMs. Utilization of the National Institute of Advanced Industrial Science and Technology's 10-kA/cm2Nb process makes it possible to accelerate the clock frequency to more than 50 GHz. We successfully demonstrated the high-speed operation of single- precision FPAs and FPMs, whose clock frequency is beyond 50 GHz, by on-chip high-speed tests. We estimate the performance and energy efficiency of SFQ FPAs and FPMs based on the designed circuits.
We are developing a large-scale reconfigurable data path (LSRDP) using single-flux-quantum (SFQ) circuits as a fundamental technology that can overcome the power-consumption and memory-wall problems in CMOS microprocessors in future high-end computing systems. An SFQ LSRDP is composed of several thousands of SFQ floating-point units connected by reconfigurable SFQ network switches to achieve high performance with low power consumption. In this study, we designed and implemented an SFQ floating-point multiplier (FPM), which is one of the key components of the SFQ LSRDP. We designed a systolic-array bit-serial half-precision FPM using the 2.5 kA/cm2Nb process. The resultant circuit area and number of Josephson junctions are 6.22 mm times 3.78 mm and 11044, respectively. The designed clock frequency is 25 GHz. We tested the circuit and confirmed the correct operation of the FPM by on-chip high-speed tests.
Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.
We are developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. In the LSRDP, an SFQ floating-point adder (FPA) is one of the main and most complicated circuit blocks. In our previous study, we implemented an SFQ half-precision (16-bit) bit-serial FPA using the ISTEC 2.5 kA/cm2standard process, and demonstrated the correct operations at 24 GHz by on-chip high-speed tests. In this study, we designed and implemented an SFQ half-precision bit-serial FPA using a cell library for the AIST 10 kA/cm2Nb nine-metal-layer process (ADP2), and carried out on-chip high speed tests. The designed FPA contains 9661 Josephson junctions and occupies a circuit area of 12.95 mm2. Its target operation frequency is 50 GHz. We have demonstrated the correct operation of the FPA at the maximum frequency of 62 GHz although there is a functional error in the design. The measured DC bias margin ranges from 102% to 108% at 50 GHz operation. The total power consumption is measured to be 2.9 mW.
Design and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10-kA/cm2 Nb Process
We have been developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. The SFQ floating-point adder (FPA) is one of the principal and most complicated circuit blocks in an LSRDP. In this study, we designed and implemented component circuits of an SFQ bit-serial half-precision FPA using the cell library for a 10-kA/cm2Nb process and performed on-chip high-speed tests. We demonstrated correct operation of the four-bit shifter for the significand at the clock frequencies of up to 76 GHz. The dependence of the measured DC bias margin on the operating frequency agrees reasonably well with the margin calculated using a digital simulation. The operation of the normalizer for the significand has been also confirmed at low speeds.
100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-kA/cm2 Niobium Process
This paper reports the design and test results of a single-flux-quantum (SFQ) bit-serial adder, which we designed with a target-clock frequency of 100 GHz, to investigate several techniques for producing ultra-high-speed computations using SFQ circuits. The bit-serial adder was designed based on a new cell library developed for the ISTEC Advanced Process, where the critical current density and McCumber-Stewart parameters of Josephson junctions were increased to 10 kA/cm2and 2.0, respectively, to obtain higher operating frequencies. In addition, we adopted a circuit-design technique based on state transitions excluding a feedback loop in a typical bit-serial adder, and redesigned the NOR gate with the McCumber-Stewart parameter increased to 4.0 to improve performance. As a result, we experimentally obtained a sufficient dc bias margin of ±18% from low frequencies to 60 GHz, and verified the correctness of operations up to 93 GHz. We also demonstrated that the introduction of a higher bias voltage or large inductors in series with bias resistors is effective for achieving faster operation.
This paper describes our programme to develop and demonstrate ultra-high performance single flux quantum (SFQ) VLSI technology that will enable superconducting digital processors for petaFLOPS-scale computing. In the hybrid technology, multi-threaded architecture, the computational engine to power a petaFLOPS machine at affordable power will consist of 4096 SFQ multi-chip processors, with 50 to 100 GHz clock frequency and associated cryogenic RAM. We present the superconducting technology requirements, progress to date and our plan to meet these requirements. We improved SFQ Nb VLSI by two generations, to a 8 kA cm −2 , 1.25 µm junction process, incorporated new CAD tools into our methodology, demonstrated methods for recycling the bias current and data communication at speeds up to 60 Gb s −1 , both on and between chips through passive transmission lines. FLUX-1 is the most ambitious project implemented in SFQ technology to date, a prototype general-purpose 8 bit microprocessor chip. We are testing the FLUX-1 chip (5K gates, 20 GHz clock) and designing a 32 bit floating-point SFQ multiplier with vector-register memory. We report correct operation of the complete stripline-connected gate library with large bias margins, as well as several larger functional units used in FLUX-1. The next stage will be an SFQ multi-processor machine. Important challenges include further reducing chip supply current and on-chip power dissipation, developing at least 64 kbit, sub-nanosecond cryogenic RAM chips, developing thermally and electrically efficient high data rate cryogenic-to-ambient input/output technology and improving Nb VLSI to increase gate density.