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IEEE Transactions on Applied Superconductivity

Towards broadband communications between RSFQ chips

Stanislav V. Polonsky, D.F. Schneider

Published Jun 1, 1997• 18 citations
Publisher

Abstract

We have investigated the applicability of Single Flux Quantum (SFQ) and Multiple Flux Quanta (MFQ) approaches to communications between RSFQ logic/memory chips. SFQ pulses can be transmitted between chips if inductive discontinuity L lies below 3-5 pH. For larger L one can employ MFQ pulses which have the same width as the SFQ pulses, but M times larger amplitude. For example, for L=20 pH, M=4 is sufficient. We have developed an MFQ driver and a receiver capable of transmitting the data in 10-20 Gbps/pin range for the use in simple flip-chip MCM packages based on Si substrates.

DOI
10.1109/77.621823

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We have investigated the applicability of Single Flux Quantum (SFQ) and Multiple Flux Quanta (MFQ) approaches to communications between RSFQ logic/memory chips. SFQ pulses can be transmitted between chips if inductive discontinuity L lies below 3-5 pH. For larger L one can employ MFQ pulses which have the same width as the SFQ pulses, but M times larger amplitude. For example, for L=20 pH, M=4 is sufficient. We have developed an MFQ driver and a receiver capable of transmitting the data in 10-20 Gbps/pin range for the use in simple flip-chip MCM packages based on Si substrates.
A novel approach to chip-to-chip communication for RSFQ technology is proposed. The main idea is to fabricate Josephson junctions on a substrate for multi-chip packaging, which equips the substrate as well as the chip with built-in active drivers and receivers. The driver on the chip is connected directly to the receiver on the substrate through a connector which can be considered as a lumped circuit element. Because the circuit is free from the impedance matching constraint, broadband chip-to-chip data transfer with wide operating margins will be realized. We have designed, simulated and optimized a chip-to-chip single flux quantum (SFQ) pulse transfer circuit. For a connector inductance of 20 pH, the bias current margins and the maximum throughput have been calculated to be /spl plusmn/24% and above 50 Gb/s, respectively.
Chip-to-chip propagation of a single flux quantum (SFQ) pulse has been demonstrated using an active multichip module (MCM) technique in which active transmitters and receivers are integrated on an MCM substrate as well as on a chip. A chip-to-chip SFQ transfer circuit has been designed and implemented by a standard Nb-trilayer process and solder-bumped flip-chip technology. The correct operation of the circuit has been confirmed by low-frequency testing. Experimental margins for the global factor for bias currents have been as large as /spl plusmn/33%.
We report a demonstration of single-flux-quantum (SFQ) pulse transmission between superconductor chips at throughputs beyond 100 Gbps. A fabrication process with a high junction critical current density of 10kA∕cm2 was used to increase the operation speed of a pulse driver and receiver. The chips were flip-chip bonded on a passive microstrip carrier using small solder bumps with diameters of 30μm. With experiments based on a ring-shaped circuit, chip-to-chip SFQ pulse transmission has been demonstrated up to 117 Gbps with an error rate of less than 10−15. The power dissipated by the driver and receiver was only 0.24μW at 117 Gbps.
We have developed an interchip data transmission scheme through passive transmission lines on a multi-chip-module (MCM) carrier and 100-/spl mu/m solder bump bonds. In rapid single flux quantum (RSFQ) logic, digital data are in the form of single flux quantum (SFQ) pulses. A reliable scheme for transmission of SFQ pulses through non-superconducting solder bumps between chips through a passive MCM substrate is yet to be established. Therefore, we have devised a scheme that converts SFQ pulses into toggles in a voltage waveform for interchip transmission. Data in the form of SFQ pulses are reconstructed from this voltage waveform using a sensitive quantizing pulse receiver. Our objective is to eliminate the need for amplification of the transmitted signal. This is achieved by increasing the receiver sensitivity. However, a sensitive receiver, a dc SQUID, may produce more than one SFQ pulse for each rising/falling edge of the voltage waveform. A simple circuit, pulse resurrection logic (PRL), is employed to discard any extra SFQ pulses. Together with the sensitive quantizer, the PRL circuit makes our scheme error tolerant. We have demonstrated the receiver operation using 3-/spl mu/m Nb RSFQ circuits at frequencies up to 20 GHz.
We report experimental results on chip-to-chip transfer of single-flux-quantum (SFQ) pulses using an active multichip module (MCM). Josephson transmitters and receivers are integrated on both a chip and an MCM substrate. An MCM consisting of a 4.8-mm chip and an 8.2-mm MCM substrate was fabricated using a 1.6-kA/cm/sup 2/ Nb-trilayer process and a solder-bumped flip-chip bonding technology. The correct operation of the circuit was confirmed by low-speed testing. Bit-error rate (BER) of the circuit was measured down to 10/sup -5/, and extrapolation of the error-function fits suggested a very small BER, lower than 10/sup -200/, at the optimum bias point. Experimental margins on the bias voltage were as large as /spl plusmn/34%.
Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>