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Physica C Superconductivity

Design and component test of RSFQ packet decoders for shift register memories

K. Fujiwara, H. Hoshina, Junichi Koshiyama, Nobuyuki Yoshikawa

Published Oct 1, 2002• 10 citations
Publisher
DOI
10.1016/s0921-4534(02)01760-4

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The lack of a high-density and high-speed memory is a serious impediment for realization of large-scale RSFQ digital systems. A shift resister memory, which has high throughput and simple circuit structure, is one candidate to overcome this drawback. We show a design framework of the shift register memory, which is usable for the high-speed register files and the main memories of the RSFQ microprocessor. The proposed system consists of an array of shift registers and a packet decoder that switches a high-speed serial data stream into the specified shift register. The target clock frequency is 16 GHz assuming 2.5 kA/cm/sup 2/ Nb standard process. We have estimated the propagation delay and the circuit area of the data-driven self-timed (DDST) packet decoder. Based on this estimation, we have also evaluated the access time and the area of the memory system. Several key components, including the one-to-two packet switch and the one-to-four DDST packet decoder, were implemented and their correct operations were confirmed.
We demonstrated a high-density shift-register-based random access memory system based on rapid single-flux-quantum (RSFQ) logic. This memory system was developed to be integrated with bit-serial RSFQ microprocessors, which are called the CORE e series. It is composed of a shift-register array to store data, a decoder to select the shift register pointed to by a given address, and mergers to output data. To achieve high density, we introduced a new memory system structure and designed compact storage elements and other peripheral components. We integrated two 256-bit memory systems (32 entries for 8-bit data and instructions each) with a CORE e microprocessor and fabricated it using the National Institute of Advanced Industrial Science and Technology 10-kA/cm2Advanced Process. The area occupied by each memory system is 2.69 mm2. We obtained correct operations for all of the addresses in low-frequency tests. The typical measured bias margin was 86%-106%.
Error rates of rapid-single-flux-quantum (RSFQ) shift register memories were investigated using a high-speed error-rate measurement system in order to demonstrate their reliability and stability. We designed and implemented an 8 times 8-bit shift register memory using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The total number of Josephson junctions including the test system is 4184, and the circuit area is 2.1 mm times 3.2 mm. We measured the error rates of every storage node by reading out the data 216times at the clock frequency of 16 GHz. The measured error rates were lower than 10-10with DC bias margin better than plusmn5%.