Adiabatic superconductor logic (ASL), including adiabatic quantum-flux-parametron (AQFP) logic, exhibits high energy efficiency because its bit energy can be decreased below the thermal energy through adiabatic switching operations. In the present paper, we present the general scaling laws of ASL and compare the energy efficiency of ASL with those of other energy-efficient logics. Also, we discuss the minimum energy-delay product (EDP) of ASL at finite temperature. Our study shows that there is a maximum temperature at which the EDP can reach the quantum limit given by ħ /2, which is dependent on the superconductor material and the Josephson junction quality, and that it is reasonable to operate ASL at cryogenic temperatures in order to achieve an EDP that approaches ħ /2.
Adiabatic superconductor logic (ASL), including adiabatic quantum-flux-parametron (AQFP) logic, exhibits high energy efficiency because its bit energy can be decreased below the thermal energy through adiabatic switching operations. In the present paper, we present the general scaling laws of ASL and compare the energy efficiency of ASL with those of other energy-efficient logics. Also, we discuss the minimum energy-delay product (EDP) of ASL at finite temperature. Our study shows that there is a maximum temperature at which the EDP can reach the quantum limit given by ħ /2, which is dependent on the superconductor material and the Josephson junction quality, and that it is reasonable to operate ASL at cryogenic temperatures in order to achieve an EDP that approaches ħ /2.
Abstract Adiabatic superconductor logic (ASL) families are energy-efficient because they can operate with a switching energy much less than the I cΦ0 product, where I c is the critical current for Josephson junctions, Φ0 is the flux quantum, and I cΦ0 is generally on the order of 10–19 J. A switching energy of 0.03I cΦ0 has been demonstrated by adiabatic quantum-flux-parametron (AQFP) logic, which indicates the possibility of extremely energy-efficient digital circuits using ASL. ASL uses signal transformers to propagate and invert the signal current; otherwise, it is difficult to design inverters. However, signal transformers are generally difficult to miniaturize. Therefore, to realize high-density and energy-efficient superconductor circuits, ASL that does not use signal transformers is required. In this paper, we propose ASL without signal transformers, which we call directly coupled quantum-flux-parametron (DQFP). DQFP logic is based on AQFP, but it can invert signal current without using signal transformers. We conducted numerical simulation of a DQFP inverter chain to show that DQFP logic can invert signal current without signal transformers, and that DQFP logic can operate adiabatically. Then, we designed and fabricated basic DQFP circuits, such as an inverter chain and a full adder. All the circuits were found to have wide operating margins. Our results indicate that DQFP logic is suitable for high-density and energy-efficient superconductor circuits.
Complementary metal-oxide-semiconductor (CMOS) circuit technology has sustainedthe exponential growth of computing power for more than 20 years. However, it hasbeen estimated that the power consumption of a next-generation supercomputer willexceed the power supplied from a single power plant. This indicates the need to dramaticallyimprove the energy efficiency of logic devices to achieve future high-endcomputers.As an extremely energy-efficient logic, we proposed and have been investigatingadiabatic quantum-flux-parametron (AQFP) devices. Due to adiabatic switching operations,its bit energy (energy dissipation per bit) can go below Ic 0, where Ic is acritical current of a Josephson junction and 0 is a single-flux-quantum (SFQ). Ic 0corresponds to the energy dissipated at every 2 phase transition in conventional nonadiabaticsuperconductor logics.We have two objectives in this study. One is to reveal physical energy bounds oncomputation through investigation of the energy efficiency of AQFP logic. The otheris to develop fundamental circuits necessary for energy-efficient computing systemsusing AQFP logic.First, we numerically and experimentally demonstrated the sub-Ic 0 bit-energyoperations of AQFP gates to show that AQFP gates operate in adiabatic modes. Weinvestigated the dependence of energy dissipation and operation margins on circuitparameters. After optimizing the parameters, we calculated the bit energy and the biterror rate at 4.2 K to verify the sub-Ic 0 bit-energy operations at a finite temperature.Additionally, we measured the bit energy of an AQFP gate using a superconductorresonator-based method.Secondly, we numerically demonstrated the sub-kBT bit-energy operations, wherekB is the Boltzmann constant and T is temperature, to show that AQFP gates can operatebeyond thermodynamic energy bounds. We investigated the dependence of energydissipation on operation frequencies and damping conditions of Josephson junctions.By using underdamped junctions, we confirmed the sub-kBT bit-energy operationsat a finite temperature thorough circuit simulation. This result indicates that thereis no minimum energy dissipation required for the operations of AQFP gates unlessthe entropy of the system decreases, which corresponds to the Landauer’s argument on the minimum energy dissipation for computation. Also, we discussed quantummechanicalenergy bounds and experimentally demonstrated AQFP gates with underdampedjunctions.Additionally, we investigated reversible computing using AQFP logic with underdampedjunctions, in order to deal with an important but unresolved question: “Isreversible computing achievable by using practical devices?” We built a purely reversiblegate by using AQFP gates, which we designated as the reversible quantumflux-parametron (RQFP) gate. We calculated its energy dissipation and confirmed thatthere is no minimum energy dissipation for reversible logic operations using RQFPgates. To the best of our knowledge, these are the first calculation results that show nominimum energy dissipation in reversible computing that use practical circuit structures.Moreover, our experimental results have demonstrated the logical and physicalreversibility of the RQFP gate. We believe that this is the first demonstration thatshows both logical and physical reversibility using practical devices.Finally, we proposed a novel energy-efficient latch for AQFP logic, which we designatedas the quantum-flux-latch (QFL). Latches are necessary circuitries in largecomputing systems but had been missing in AQFP logic. We discussed its energyefficiency through simulation and experimentally demonstrated correct operations ofthe QFL and a 1-bit shift register using QFLs. Also, we proposed high-speed test circuitsusing QFLs and experimentally demonstrated logic operations of AQFP circuitsat high speed.We strongly believe that our results showed the extremely high energy efficiency ofAQFP logic. These results will move the AQFP logic to practical usage as extremelyenergy-efficient integrated circuits.
Adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic. The advantage of AQFP is that the switching energy can be reduced by lowering operation frequencies or by increasing the quality factors of Josephson junctions, while keeping the energy barrier height much larger than thermal energy. In other words, both low energy dissipation and low bit error rates (BERs) can be achieved. In this paper, we report the first measurement results of the low BERs of AQFP logic. We used a superconductor voltage driver with a stack of dc superconducting-quantum-interference-devices to amplify the logic signals of AQFP gates into mV-range voltage signals for the BER measurement. Our measurement results showed 3.3 dB and 2.6 dB operation margins, in which BERs were less than 10−20, for 1 Gbps and 2 Gbps data rates, respectively. While the observed BERs were very low, the estimated switching energy for the 1-Gbps operation was only 2 zJ or 30kBT, where kB is the Boltzmann's constant and T is the temperature. Unlike conventional non-adiabatic logic, BERs are not directly associated with switching energy in AQFP.
Adiabatic quantum-flux-parametron (AQFP) logic can achieve high energy-efficiency. The bit energy and bit-error-rate (BER) of AQFP gates with under-damped Josephson junctions were simulated. The results indicate that the bit energy reaches 12 yJ, which is only 20% of the thermal energy at 4.2 K, using unshunted 50-μA junctions and excitation currents with a rise/fall time of 2000 ps. Although the bit energy is extremely small, the bias margin, where the BER is less than 10−23, is approximately ±22%. These results indicate there is no minimum energy limitation for the operation of AQFP gates unless the entropy of the system decreases.
Adiabatic quantum flux parametron (AQFP) is a very energy-efficient superconductor logic. In AQFP logic, dynamic energy dissipation can be drastically reduced due to adiabatic switching operations using ac excitation currents. In the present study, we evaluated circuit yields using a large-scale AQFP circuit composed of as many as 10,000 AQFP gates with approximately 20,000 Josephson junctions. We measured eleven chips from four wafers and obtained circuit yields of 48% for 1,000-gate circuits and 22% for 10,000-gate circuits, respectively. In all the circuits, which worked correctly, the margins of excitation currents were as wide as approximately ±20%.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The latency of AQFP circuits is relatively long compared to that of other superconductor logic families and thus such circuits require low-latency clocking schemes. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current, and demonstrated a simple AQFP buffer chain that adopts delay-line clocking. However, it is unclear whether more complex AQFP circuits can adopt delay-line clocking. In the present study, we demonstrate AQFP logic gates (AND and XOR gates) that use delay-line clocking as a step towards implementing large-scale AQFP circuits with delay-line clocking. AND and XOR gates with a latency of approximately 20 ps per gate are shown to operate at up to 5 and 4 GHz, respectively, in experiments. We also demonstrate that delay-line clocking enables phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. The results indicate that delay-line clocking can enable low-latency, low-energy, large-scale AQFP circuits.