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IEEE Transactions on Communications

Two reliability-based iterative majority-logic decoding algorithms for LDPC codes

Qin Huang, Jaewook Kang, Li Guo Zhang, Shu Lin, Khaled Abdel-Ghaffar

Published Dec 1, 2009• 75 citations
Publisher

Abstract

This paper presents two novel reliability-based iterative majority-logic decoding algorithms for LDPC codes. Both algorithms are binary message-passing algorithms and require only logical operations and integer additions. Consequently, they can be implemented with simple combinational logic circuits. They either outperform or perform just as well as the existing weighted bit-flipping or other reliability-based iterative decoding algorithms for LDPC codes in error performance with a faster rate of decoding convergence and less decoding complexity. Compared to the sum-product algorithm for LDPC codes, they offer effective trade-offs between performance and decoding complexity.

DOI
10.1109/tcomm.2009.12.080493

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IEEE Transactions on Communications•Sep 29, 2010•91 citations
This paper presents two novel reliability-based iterative majority-logic decoding algorithms for LDPC codes. Both algorithms are binary message-passing algorithms and require only logical operations and integer additions. Consequently, they can be implemented with simple combinational logic circuits. They either outperform or perform just as well as the existing weighted bit-flipping or other reliability-based iterative decoding algorithms for LDPC codes in error performance with a faster rate of decoding convergence and less decoding complexity. Compared to the sum-product algorithm for LDPC codes, they offer effective trade-offs between performance and decoding complexity.
This paper presents two novel iterative reliability-based majority-logic algorithms for decoding LDPC codes. Both algorithms are binary message-passing algorithms and require only logical operations and integer additions. Consequently, they can be implemented with simple combinational logic circuits. They either outperform or perform just well as the existing weighted bit-flipping or other reliability-based decoding algorithms for LDPC codes in error performance with a faster rate of decoding convergence and less decoding complexity. Compared to the sum-product algorithm for LDPC codes, they offer effective trade-offs between performance and decoding complexity.
This paper presents a majority-logic based message-passing algorithm for decoding non-binary LDPC codes. Recently, many majority-logic decoding (MLGD) algorithms make huge efforts on reducing the computational complexity for decoding non-binary LDPC codes. Inspired by one step majority-logic decoding and q-ary sum-product algorithm, we devise a novel iterative double-reliability-based (IDRB) MLGD algorithm which carries out an efficient trade-off between decoding computational complexity and error performance. The proposed algorithm achieves a remarkable enhancement on error correct ability and yet requires only integer operations and finite field operations. Simulation results on two NB-LDPC codes show that we succeed in achieving significant coding gain compared with IHRB- and ISRB-MLGD with limited complexity increase.
An attenuated iterative reliability-based majority-logic (AIML) decoding algorithm for low-density parity-check (LDPC) codes is proposed. This novel algorithm is devised based on the orthogonal check-sums of the one-step majority-logic decoding algorithm in conjunction with certain of reliability measures of the received symbols. The computation of reliability measure of the syndrome sum is refined by introducing an attenuation factor. Simulation results show that in binary input-additive white Gaussian noise channel, the AIML algorithm outperforms other popular iterative reliability-based majority-logic decoding algorithms with a slight increase in computational complexity. With maximum iterations five and fifty, the AIML algorithm can achieve almost identical error performance for LDPC codes. No error floor effect can be observed for AIML algorithm down to the bit error rate (BER) of 10−8, while error floor appears for sum product algorithm (SPA) around the BER of 10−7even with maximum iteration 100. The inherent feature of parallel decoding for AIML algorithm enforces the decoding speed in contrast to those serial decoding schemes, such as weighted bit-flipping algorithm.
A modified reliability-based iterative majority-logic decoding (MRBI-MLGD) algorithm for two classes of structured LDPC codes is presented based on a recent work by Huang et al. Compared with the original one, the modified algorithm has better performance with slightly increased complexity. Then a reliability-based iterative min-sum decoding (RBI-MSD) algorithm is presented. For the presented RBI-MSD algorithm, reliability-based integer messages are processed and exchanged between variable nodes and check nodes. The main computations include only binary logical operations and integer additions. Different from the conventional min-sum algorithm, the variable nodes pass full messages rather than extrinsic messages to check nodes. This can reduce the memory loads and the computational complexity but with a little (or negligible) performance degradation. Simulation results show that, compared with the (M)RBI-MLGD algorithms, the presented RBI-MSD algorithm achieves better error performance, faster decoding convergence rate and fewer quantization bits with moderate increased computational complexity. Furthermore, the RBI-MSD algorithm is also applicable to decoding random LDPC codes, a distinct difference from the (M)RBI-MLGD algorithms. Finally, we point out that the scaling factors employed in the MRBI-MLGD algorithm and the RBI-MSD algorithm can be optimized using discretized density evolution.
In this paper, we present an iterative reliability-based modified majority-logic decoding algorithm for two classes of structured low-density parity-check codes. Different from the conventional modified one-step majority-logic decoding algorithms, we design a turbo-like iterative strategy to recover the performance degradation caused by the simply flipping operation. The main computational loads of the presented algorithm include only binary logic and integer operations, resulting in low decoding complexity. Furthermore, by introducing the iterative set, a very small proportion (less than 6%) of variable nodes are involved in the reliability updating process, which can further reduce the computational complexity. Simulation results show that, combined with the factor correction technique and a well-designed non-uniform quantization scheme, the presented algorithm can achieve a significant performance improvement and a fast decoding speed, even with very small quantization levels (3-4 bits resolution). The presented algorithm provides a candidate for trade-offs between performance and complexity.