Confinement‐Engineered CdSe Quantum‐Rod Qubits with Pareto‐Optimized Coherence, Gate Speed, and Fabrication Robustness
Polynice Diffo Nguedia, A. J. Fotué, Maurice Tiotsop
ABSTRACT A confinement‐engineered design framework is developed for CdSe quantum‐rod qubits by treating the radius and aspect ratio as independent control parameters. The qubit is encoded in the two lowest axially confined orbital states; finite‐barrier and dielectric‐mismatch corrections () shift the coherence ridge by only nm without altering the Pareto topology, as confirmed by a new corrected sub‐panel (Figure 3b). Phonon‐induced relaxation is modeled through deformation‐potential, piezoelectric, and Fröhlich channels within a Born–Markov framework whose validity is verified throughout the design space. Mapping the full plane reveals a coherence ridge near nm, , where the phonon‐relaxation‐limited approaches 100 ns at 4 K as an upper bound. The optically driven Rabi frequency increases with rod length, producing a Pareto trade‐off between coherence and gate speed. A four‐parameter sensitivity analysis (Table and Figure ) confirms the ridge and Pareto topology are robust to parameter variations. A Monte Carlo analysis with log‐normal size distributions (Figure ) validates the fabrication robustness metric and confirms the target nm, . A speed‐favored Pareto knee near nm, achieves GHz with ns and gate fidelities –0.99 after DRAG pulse shaping. An experimental control protocol and scalability limitations are discussed.
Advanced Quantum Technologies•Jul 1, 2026•0 citations