Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

International Symposium on Turbo Codes and Iterative Information Processing

Faulty stochastic LDPC decoders over the binary symmetric channel

Christiane L. Kameni Ngassa, Valentin Savin, David Declercq

Published Aug 1, 2014• 3 citations
Publisher

Abstract

The analysis of error correction decoders running on faulty hardware has attracted an increasing interest in recent years, due to the inherent unreliability of emerging nanodevices. In this paper we investigate the performance of the stochastic decoder running on faulty hardware. To this end, we first introduce two error models to describe the noisy components of the decoder. We then provide a finite-length statistical analysis for each error model and, based on the obtained performance, we conclude that stochastic decoders have an inherent fault tolerant capability.

DOI
10.1109/istc.2014.6955096

Related papers

Analysis of Min-Sum based decoders implemented on noisy hardware

Christiane L. Kameni Ngassa, Valentin Savin, David Declercq

Motivated by the problem of designing fault-tolerant memories built out from unreliable components, this paper investigates the performance of two noisy Min-Sum-based decoders on Binary Symmetric Channels. We analyze the performance of the noisy Min-Sum decoder in terms of useful regions and target bit-error rate threshold values, derived by using “noisy” density evolution equations. We also present the finite length performance of two Min-Sum based decoders, and point out the excellent performance of the noisy Self-Corrected Min-Sum decoder, which exhibits almost the same performance as the noiseless decoder.

Asilomar Conference on Signals, Systems and Computers (ACSSC)•Nov 1, 2013•7 citations

Min-Sum-based decoders running on noisy hardware

Christiane L. Kameni Ngassa, Valentin Savin, David Declercq

This paper deals with Low-Density Parity-Check decoders running on noisy hardware. This represents an unconventional paradigm in communication theory, since it is traditionally assumed that the error correction decoder operates on error-free devices and the randomness (in the form of noise and/or errors) exists only in the transmission channel. However, with the advent of nanoelectronics, it starts to be widely accepted that the future generations of circuits and systems will need to reliability compute and solve statistical inferences, by making use of unreliable “noisy” components. It is then critical to properly evaluate the robustness of the existing decoders in the presence of an additional source of noise at the circuit level. To this end, we first introduce a new error model approach and carry out the “noisy” density evolution analysis of the fixed-point Min-Sum decoding. Then, for different parameters of the noisy components of the decoder, we determine the range of the signal-to-noise ratio values for which the decoder is able to achieve a target bit error rate performance. Finally, we evaluate the finite-length performance of the Min-Sum and two other Min-Sum-based decoders running on noisy hardware.

Globecom•Dec 1, 2013•42 citations

Performance of LDPC Codes Under Faulty Iterative Decoding

Lav R. Varshney

Departing from traditional communication theory where decoding algorithms are assumed to perform without error, a system where noise perturbs both computational devices and communication channels is considered here. This paper studies limits in processing noisy signals with noisy circuits by investigating the effect of noise on standard iterative decoders for low-density parity-check (LDPC) codes. Concentration of decoding performance around its average is shown to hold when noise is introduced into message-passing and local computation. Density evolution equations for simple faulty iterative decoders are derived. In one model, computing nonlinear estimation thresholds shows that performance degrades smoothly as decoder noise increases, but arbitrarily small probability of error is not achievable. Probability of error may be driven to zero in another system model; the decoding threshold again decreases smoothly with decoder noise. As an application of the methods developed, an achievability result for reliable memory systems constructed from unreliable components is provided.

IEEE Transactions on Information Theory•Jun 21, 2011•115 citations

Finite alphabet iterative decoders robust to faulty hardware: Analysis and selection

Elsa Dupraz, David Declercq, Bane V. Vasic +1 more

In this paper, we analyze Finite Alphabet Iterative Decoders (FAIDs) running on faulty hardware. Under symmetric error models at the message level, we derive the noisy Density Evolution equations, and introduce a new noisy threshold phenomenon (called functional threshold), which accurately characterizes the convergence behavior of LDPC code ensembles under noisy-FAID decoding. The proposed functional threshold is then used to identify FAIDs which are particularly robust to the transient hardware noise. Finite-length simulations are drawn to verify the validity of the asymptotical study.

International Symposium on Turbo Codes and Iterative Information Processing•Aug 1, 2014•14 citations

Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures

Srdan S. Brkic, Predrag Ivaniš, Bane V. Vasic

In this paper we analyze the effect of hardware unreliability to performance of bit-flipping decoders of low-density parity-check (LDPC) codes. We apply expander arguments to show that the simple parallel bit flipping decoder, built partially from faulty gates, can correct a linear fraction of worst case channel errors, when gate failures are correlated and dependent on the switching activity of logic gates. In addition, we provide a lower bound on the guaranteed error correction of LDPC codes with left degree of at least eight.

IEEE International Symposium on Information Theory (ISIT)•Jul 1, 2016•5 citations

Analysis and Design of Finite Alphabet Iterative Decoders Robust to Faulty Hardware

Elsa Dupraz, David Declercq, Bane V. Vasic +1 more

This paper addresses the problem of designing low-density parity check decoders robust to transient errors introduced by faulty hardware. We assume that the faulty hardware introduces errors during the message-passing updates, and we propose a general framework for the definition of the message update faulty functions. Within this framework, we define symmetry conditions for the faulty functions and derive two simple error models used in the analysis. With this analysis, we propose a new interpretation of the functional density evolution threshold introduced by Kameni et al. in the recent literature and show its limitations in the case of highly unreliable hardware. However, we show that under restricted decoder noise conditions, the functional threshold can be used to predict the convergence behavior of finite alphabet iterative decoders (FAIDs) under faulty hardware. In particular, we reveal the existence of robust and nonrobust FAIDs and propose a framework for the design of robust decoders. We finally illustrate robust- and nonrobust-decoder behaviors of finite-length codes using Monte Carlo simulations.

arXiv:1410.2291•IEEE Transactions on Communications•Jul 7, 2015•20 citations
The analysis of error correction decoders running on faulty hardware has attracted an increasing interest in recent years, due to the inherent unreliability of emerging nanodevices. In this paper we investigate the performance of the stochastic decoder running on faulty hardware. To this end, we first introduce two error models to describe the noisy components of the decoder. We then provide a finite-length statistical analysis for each error model and, based on the obtained performance, we conclude that stochastic decoders have an inherent fault tolerant capability.
Motivated by the problem of designing fault-tolerant memories built out from unreliable components, this paper investigates the performance of two noisy Min-Sum-based decoders on Binary Symmetric Channels. We analyze the performance of the noisy Min-Sum decoder in terms of useful regions and target bit-error rate threshold values, derived by using “noisy” density evolution equations. We also present the finite length performance of two Min-Sum based decoders, and point out the excellent performance of the noisy Self-Corrected Min-Sum decoder, which exhibits almost the same performance as the noiseless decoder.
This paper deals with Low-Density Parity-Check decoders running on noisy hardware. This represents an unconventional paradigm in communication theory, since it is traditionally assumed that the error correction decoder operates on error-free devices and the randomness (in the form of noise and/or errors) exists only in the transmission channel. However, with the advent of nanoelectronics, it starts to be widely accepted that the future generations of circuits and systems will need to reliability compute and solve statistical inferences, by making use of unreliable “noisy” components. It is then critical to properly evaluate the robustness of the existing decoders in the presence of an additional source of noise at the circuit level. To this end, we first introduce a new error model approach and carry out the “noisy” density evolution analysis of the fixed-point Min-Sum decoding. Then, for different parameters of the noisy components of the decoder, we determine the range of the signal-to-noise ratio values for which the decoder is able to achieve a target bit error rate performance. Finally, we evaluate the finite-length performance of the Min-Sum and two other Min-Sum-based decoders running on noisy hardware.
Departing from traditional communication theory where decoding algorithms are assumed to perform without error, a system where noise perturbs both computational devices and communication channels is considered here. This paper studies limits in processing noisy signals with noisy circuits by investigating the effect of noise on standard iterative decoders for low-density parity-check (LDPC) codes. Concentration of decoding performance around its average is shown to hold when noise is introduced into message-passing and local computation. Density evolution equations for simple faulty iterative decoders are derived. In one model, computing nonlinear estimation thresholds shows that performance degrades smoothly as decoder noise increases, but arbitrarily small probability of error is not achievable. Probability of error may be driven to zero in another system model; the decoding threshold again decreases smoothly with decoder noise. As an application of the methods developed, an achievability result for reliable memory systems constructed from unreliable components is provided.
In this paper, we analyze Finite Alphabet Iterative Decoders (FAIDs) running on faulty hardware. Under symmetric error models at the message level, we derive the noisy Density Evolution equations, and introduce a new noisy threshold phenomenon (called functional threshold), which accurately characterizes the convergence behavior of LDPC code ensembles under noisy-FAID decoding. The proposed functional threshold is then used to identify FAIDs which are particularly robust to the transient hardware noise. Finite-length simulations are drawn to verify the validity of the asymptotical study.
In this paper we analyze the effect of hardware unreliability to performance of bit-flipping decoders of low-density parity-check (LDPC) codes. We apply expander arguments to show that the simple parallel bit flipping decoder, built partially from faulty gates, can correct a linear fraction of worst case channel errors, when gate failures are correlated and dependent on the switching activity of logic gates. In addition, we provide a lower bound on the guaranteed error correction of LDPC codes with left degree of at least eight.
This paper addresses the problem of designing low-density parity check decoders robust to transient errors introduced by faulty hardware. We assume that the faulty hardware introduces errors during the message-passing updates, and we propose a general framework for the definition of the message update faulty functions. Within this framework, we define symmetry conditions for the faulty functions and derive two simple error models used in the analysis. With this analysis, we propose a new interpretation of the functional density evolution threshold introduced by Kameni et al. in the recent literature and show its limitations in the case of highly unreliable hardware. However, we show that under restricted decoder noise conditions, the functional threshold can be used to predict the convergence behavior of finite alphabet iterative decoders (FAIDs) under faulty hardware. In particular, we reveal the existence of robust and nonrobust FAIDs and propose a framework for the design of robust decoders. We finally illustrate robust- and nonrobust-decoder behaviors of finite-length codes using Monte Carlo simulations.