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International Symposium on Information Theory and its Applications

Gradient descent bit flipping algorithms for decoding LDPC codes

Tadashi Wadayama, K. Nakamura, Masayuki Yagita, Yuuki Funahashi, Shogo Usami, Ichi Takumi

Published Dec 1, 2008• 33 citations
Publisher

Abstract

A novel class of bit-flipping (BF) algorithms for decoding low-density parity-check (LDPC) codes is presented. The proposed algorithms, which are called gradient descent bit flipping (GDBF) algorithms, can be regarded as simplified gradient descent algorithms. Based on gradient descent formulation, the proposed algorithms are naturally derived from a simple nonlinear objective function.

DOI
10.1109/isita.2008.4895387

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A novel class of bit-flipping (BF) algorithms for decoding low-density parity-check (LDPC) codes is presented. The proposed algorithms, which are called gradient descent bit flipping (GDBF) algorithms, can be regarded as simplified gradient descent algorithms. Based on gradient descent formulation, the proposed algorithms are naturally derived from a simple nonlinear objective function.
Gradient descent bit-flipping (GDBF) decoding for low-density parity-check (LDPC) codes has gained great attentions because of low complexity and relatively good performance. However, the performance of the GDBF decoding is still much poorer than that of the MS algorithm. To further improve the performance, the iterative decoding process is introduced to GDBF decoding in this paper. At the end of each iteration, the latest information is used to update the reliability of the flipped bit, by which its reliability is greatly improved. Simulation results indicate that the proposed algorithm has about 0.4 dB performance gains compared to GDBF. Meanwhile, there is small computational complexity increased.
Low-Density Parity-Check (LDPC) codes have capacity-approaching error-correction performance which makes them popular in communication system. Gradient descent bit flipping (GDBF) algorithms show an error correction capability superior to most known BF algorithms. In this paper, we propose an improved gradient descent bit flipping (IGDBF) algorithm for LDPC codes on BSC channel. Compared to GDBF algorithm, the proposed algorithm reconstructs the composition of energy function, and adds a penalty term to help it converge. Simulations show that the proposed algorithm has good performance and fast convergence rate.
The Gradient descent bit flipping (GDBF) algorithm is a representative approach for decoding low-density parity-check (LDPC) codes, which offers a good tradeoff between decoding performance and complexity. Unfortunately, the decoding performance of GDBF algorithm degenerates dramatically for structured LDPC codes due to their large column weight. To address the above issue, we propose to improve GDBF algorithm by introducing a weighted parameter in the energy function of each bit. Specifically, this parameter compensates for the computational error of the energy function due to the large column weight of the parity-check matrices of structured LDPC codes. Moreover, the flipping number of each bit in the iterative process is included in the energy function to avoid consecutive bit flips in the decoding. Simulation results on typical structured LDPC codes indicate that the performance of the proposed algorithm is better than the standard GDBF algorithm at the cost of slight increment in the algorithmic complexity. The increase operations can be easily implemented, which indicates the proposed algorithm is suitable for practical purposes.
It is known that the Gradient descent bit flipping (GDBF) algorithm is an effective hard-decision decoding algorithm for low-density parity-check (LDPC) codes. However, trapping in a local maximum limits its error-rate performance. This paper presents a modified GDBF scheme that can mitigate the trapping problem and hence can improve the error-rate performance. Compared to the conventional GDBF algorithm, the proposed method is able to improve the decoding performance of 0.3dB for an (18582, 16626) code. The (18582, 16626) LDPC decoder integrates 636k logic gates and achieves a throughput of 12.4 Gbps at a clock frequency of 200 MHz in a 90nm process.