Non-binary LDPC codes are promising error correcting codes for short and moderate block lengths. These codes demonstrate interesting performances in high order fields, though are more complex to decode. As for binary LDPC codes, decoding scheduling can be optimized to improve performance. In this paper, a simulation-based approach is used for different scheduling policies in the non-binary case in order to point out possible performance gains for these codes. An optimization of decoding scheduling is also proposed and exhibits about 20% complexity reduction in error-floor region, thus promising interesting gains if combined with advanced dynamic scheduling strategies.
Non-binary LDPC codes are promising error correcting codes for short and moderate block lengths. These codes demonstrate interesting performances in high order fields, though are more complex to decode. As for binary LDPC codes, decoding scheduling can be optimized to improve performance. In this paper, a simulation-based approach is used for different scheduling policies in the non-binary case in order to point out possible performance gains for these codes. An optimization of decoding scheduling is also proposed and exhibits about 20% complexity reduction in error-floor region, thus promising interesting gains if combined with advanced dynamic scheduling strategies.
Non-binary LDPC codes are promising error cor- recting codes for short and moderate block lengths. These codes demonstrate interesting performances in high order fields, though are more complex to decode. As for binary LDPC codes, decoding scheduling can be optimized to improve performance. In this paper, a simulation-based approach is used for different scheduling policies in the non-binary case in order to point out possible performance gains for these codes. An optimization of decoding scheduling is also proposed and exhibits about 20% complexity reduction in error-floor region, thus promising interesting gains if combined with advanced dynamic scheduling strategies. I. INTRODUCTION Channel coding has seen important developments over the last two decades. Thanks to the introduction of advanced error- correcting codes, initiated by Turbo-codes in the early 90's, and to the use of iterative decoding techniques, Shannnon- limit performance has been closely approached. Low-Density Parity-Check (LDPC) codes, first introduced by Gallager (1) in the 60's, were rediscovered by Mackay and Neal (2) in 1996. Excellent error-correcting performance for long block lengths (3) position LDPC codes as an important candidate for advanced communication systems, already adopted in different standards, such as DVB-S2, IEEE 802.16 and 802.11n. How- ever, as codewords become shorter, LDPC performance gains are generally less satisfying. Non-binary LDPC codes, though more complex, proved to significantly improve performance for moderate and short blocklengths (4), (5). The use of a high order alphabet also suggests matching it with the modulation alphabet: LDPC codes over a 16�elements Galois field for example can be naturally mapped in 16�QAM modulated symbols. This would avoid the bit-to-symbol performance loss, especially when having a frequency selective channel, as non- binary encoding can reduce channel memory effect (6). This use of non-binary LDPC codes is thus very promising for high data rate communications, especially when complexity reduc- tion techniques are adopted, either for decoding update rules or scheduling policy. Previous work on scheduling strategies for the binary case can be found in (7). In this paper, we will first address a brief overview of decoding techniques for LDPC codes over high order extension fields. Then, scheduling strategies and effects will be compared for the non-binary case. A simulation-based approach will also be detailed to suggest new scheduling policies, and results from an optimized scheduling will be presented. The paper will be concluded by some remarks and suggestions towards future works.
Non-binary LDPC codes have interesting performances, especially for short to moderate blocklengths. The decoding schedule of these codes decoding, similarly to the binary case, has an important impact on the decoder's behaviour and should be carefully designed. This paper studies and optimizes the layered scheduling of non-binary LDPC codes following two approaches: A static approach, defining an optimized permanent scheduling for the decoder independently of its entries or state, and a dynamic approach adapting the scheduling on the fly following the decoder's convergence. These two approaches show either a reduction in the number of iterations of about 18% or a reduction in signal to noise ratio of about 0.05dB.
Recently low-density parity check (LDPC) codes have been applied in more areas, and the research of non-binary LDPC codes has become more significant. In this paper, we establish a dynamic scheduling strategy to reduce complexity of non-binary LDPC codes decoding, and choose extended min-sum algorithm as the model. The dynamic scheduling strategy is based on the idea of nodes reliability. When decoding, we select a part of check nodes to update messages in real time according to the reliability rules, and only the variable nodes getting new messages can participate in the message propagation. Compared with usual standard flooding scheduling, this dynamic scheduling strategy can reduce decoding complexity effectively. We also optimize the message of variable nodes according to reliability, which ensure that the error correction performance of decoding algorithm is not affected. Our simulations over a BPSK-AWGN channel show that this dynamic scheduling strategy can reduce complexity in non-binary LDPC codes belief propagation decoding without affecting error correction performance.
Non-binary LDPC codes are promising error correcting techniques with very good performance, especially for high order fields. Using higher order fields enhances performance but, at the same time, increases decoding complexity. Several methods have been proposed to reduce this complexity, such as sub-optimal decoding algorithms or techniques aiming at reducing the number of iterations. In this paper, a technique for selective check nodes update is presented enabling a complexity reduction at the level of iteration in the non-binary case. More than 35% of complex updates can be saved in a large SNR region, with parameters that can be tuned according to the desired complexity/performance ratio.
Scheduling strategy is considered an important aspect of belief-propagation (BP) decoding of low-density parity-check (LDPC) codes because it affects the decoder's convergence rate, decoding complexity and error-correction performance. In this paper, we propose two new scheduling strategies for the BP decoding of non-binary LDPC (NB-LDPC) codes. Both the strategies are devised based on the concept of check node reliability and employ a heuristically defined threshold which can adapt to the communication channel variations. As the scheduling strategies only update a subset of the check nodes in each iteration, they result in reduced iteration cost. Furthermore, since the BP performs suboptimally for finite-length LDPC codes, especially for short-length LDPC codes, by enhancing the message propagation over the Tanner Graphs of short-length NB-LDPC codes, the new scheduling strategies can even improve the error-correction performances of BP decoding. Simulation results demonstrate that the new scheduling strategies provide good performance/complexity tradeoffs.
Low-Density Parity-Check (LDPC) codes are usually decoded by running an iterative belief-propagation (BP), or message-passing, algorithm over the factor graph of the code. The message-passing schedule of the BP algorithm significantly affects the performance of the LDPC decoder. The authors recently presented a novel message-passing schedule, called Informed Dynamic Scheduling (IDS), that selects the message-passing schedule according to the observed rate of change of the messages. IDS yields a lower error-rate performance than traditional message-passing schedules (such as flooding and LBP) because it solves traditional trapping-set errors. However, for short-blocklength LDPC codes, IDS algorithms present non-trapping-set errors in the error floor region. This paper presents a careful analysis of those errors and proposes mixed scheduling strategies, combining LBP with IDS, that solve these non-trapping-set errors. Also, we will show that some lower-complexity techniques, such as mixed scheduling, perform close to the best IDS strategies for larger-blocklength codes.