Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE International Symposium on Information Theory (ISIT)

Structured eIRA codes with low floors

Yifei Zhang, W.E. Ryan, Yan Li

Published Jan 1, 2005• 32 citations
Publisher

Abstract

In a recent paper, Yang et al. presented the class of extended irregular repeat-accumulate (eIRA) codes which are efficiently encodable LDPC codes possessing very low error-rate floors and are appropriate for code rates 1/2 or greater. While efficiently encodable, the left-most (n-k)-by-k submatrix of an eIRA code parity-check matrix is random in nature, making efficient decoder implementation problematic. In the present paper, we present structured eIRA codes. We first present some ensemble results for the general class of eIRA codes, after which the subclass of structured eIRA (SeIRA) codes is defined. Software- and hardware-based performance results for SeIRA code designs (rates 0.5 to 0.9) are then presented.

DOI
10.1109/isit.2005.1523317

Related papers

eIRA LDPC Codes on FPGA

John Ding, Michael Yang

eIRA codes are iteratively decodable low-density parity-check (LDPC) codes. They not only offer superior performance to alternative approaches, but they allow linear-time encoding. Well-designed eIRA codes also achieve extremely low error-rate floors. In this letter, we successfully implement a common FPGA platform for eIRA codes. As a demonstration, we took an example parity-check matrix from Example 4 in . For a maximum of seven iterations and 7 bits precision, the error-rate degradation is less than two tenths of a decibel compared to the double precision floating point result. It is important to note that there is no error rate floor close to BER of 10-12. Such a performance is often requested in practical applications, but has never been achieved by graphic codes in the literature so far as we know.

IEEE Communications Letters•Apr 26, 2011•4 citations

Design of q-ary Irregular Repeat-Accumulate Codes

Wei Lin, Baoming Bai, Ying Li +1 more

This paper is concerned with the construction of a class of nonbinary irregular repeat accumulate (IRA) codes. Since they are defined on the finite field GF(q) (q>2), we will refer to the constructed codes as q-ary IRA (QIRA) codes. While preserving the excellent error correcting capability of q-ary LDPC codes, QIRA codes can be efficiently encoded like conventional binary IRA codes. By adopting the progressive edge growth (PEG) algorithm to construct the parity check matrices, we can achieve the increased girth of their factor graphs and improved decoding performance. Simulation results show that, using the sum-product algorithm on GF(q), QIRA codes outperform binary LDPC codes and turbo codes in terms of bit error ratio and frame error ratio on AWGN channels. Especially, they could achieve excellent error performance when combined with high order modulations. Feasibility study indicates, with the use of the extended min-sum (EMS) decoding algorithm, QIRA codes are competitive candidates for practical applications.

International Conference on Advanced Information Networking and Applications (AINA)•Jan 1, 2009•8 citations

Design of Low-Floor Quasi-Cyclic IRA Codes and Their FPGA Decoders

Yifei Zhang

Low-density parity-check (LDPC) codes have been intensively studied in the past decade for their capacity-approaching performance. LDPC code implementation complexity and the error-rate floor are still two significant unsolved issues which prevent their application in some important communication systems. In this dissertation, we make efforts toward solving these two problems by introducing the design of a class of LDPC codes called structured irregular repeat-accumulate (S-IRA) codes. These S-IRA codes combine several advantages of other types of LDPC codes, including low encoder and decoder complexities, flexibility in design, and good performance on different channels. It is also demonstrated in this dissertation that the S-IRA codes are suitable for rate-compatible code family design and a multi-rate code family has been designed which may be implemented with a single encoder/decoder.The study of the error floor problem of LDPC codes is very difficult because simulating LDPC codes on a computer at very low error rates takes an unacceptably long time. To circumvent this difficulty, we implemented a universal quasi-cyclic LDPC decoder on a field programmable gate array (FPGA) platform. This hardware platform accelerates the simulations by more than 100 times as compared to software simulations. We implemented two types of decoders with partially parallel architectures on the FPGA: a circulant-based decoder and a protograph-based decoder. By focusing on the protograph-based decoder, different soft iterative decoding algorithms were implemented. It provides us with a platform for quickly evaluating and analyzing different quasi-cyclic LDPC codes, including the S-IRA codes. A universal decoder architecture is also proposed which is capable of decoding of an arbitrary LDPC code, quasi-cyclic or not. Finally, we studied the low-floor problem by focusing on one example S-IRA code. We identified the weaknesses of the code and proposed several techniques to lower the error floor. We successfully demonstrated in hardware that it is possible to lower the floor substantially by encoder and decoder modifications, but the best solution appeared to be an outer BCH code.

•Jan 1, 2007•5 citations

Accumulate-Repeat-Accumulate-Accumulate Codes

D. Divsalar, Samuel J. Dolinar, Jeremy Thorpe

Accumulate-repeat-accumulate-accumulate (ARAA) codes have been proposed, inspired by the recently proposed accumulate-repeat-accumulate (ARA) codes. These are error-correcting codes suitable for use in a variety of wireless data-communication systems that include noisy channels. ARAA codes can be regarded as serial turbolike codes or as a subclass of low-density parity-check (LDPC) codes, and, like ARA codes they have projected graph or protograph representations; these characteristics make it possible to design high-speed iterative decoders that utilize belief-propagation algorithms. The objective in proposing ARAA codes as a subclass of ARA codes was to enhance the error-floor performance of ARA codes while maintaining simple encoding structures and low maximum variable node degree.

•Sep 1, 2007•0 citations

Regular {4, 8} LDPC Codes and Their Lowerror Floors

Chad A. Cole, Stephen G. Wilson, E.K. Hall +1 more

Regular LDPC codes are a special class of low-density codes having an equal number of ones in each row and column of the parity check matrix describing the linear code. The uniform structure of regular LDPC codes allows a practical hardware implementation which can efficiently utilize the inherent parallelism of the message passing algorithm (MPA) commonly used to decode low-density codes. The class of {3,6} LDPC codes has been extensively studied and they have been proven to provide very good error performance, especially at lower SNR. {4,8} codes have not been analyzed nearly as much in the literature, mainly because their 'threshold,' the SNR where the waterfall region of the error performance curve begins, is typically a quarter of a dB or so worse than for comparable-length {3,6} codes. It has been proposed that {4,8} codes have better high SNR behavior, but until recently it was not possible to verify this conjecture. A new technique which can efficiently find error floors of LDPC codes now has the ability to illuminate just how good {4,8} codes are in the high SNR region-a result which is of great interest for many practical applications. This paper will analyze the error floor characteristics of some {4,8} codes and provide a simple algorithm for designing {4,8} codes with low error floors. A newly-designed rate-1/2 (1200,600) {4,8} code with a vastly superior error floor compared to codes of similar parameters is introduced

IEEE Military Communications Conference (MILCOM)•Oct 1, 2006•5 citations

Design methods for irregular repeat accumulate codes

Aline Roumy, Souad Guemghar, Giuseppe Caire +1 more

We optimize the low-complexity random-like ensemble of irregular repeat accumulate (IRA) codes for binary-input symmetric channels in the large blocklength limit. IRA codes Jin, H et al. (2000) are special subclasses of both irregular LDPCs and irregular turbo codes. We present numerical results for the BIAWGNC and formulate the density evolution (DE) Richardson, TJ et al. (2001) for IRA codes. We study the stability condition of the fixed-point corresponding to zero BER.

IEEE International Symposium on Information Theory (ISIT)•Jan 1, 2003•11 citations
In a recent paper, Yang et al. presented the class of extended irregular repeat-accumulate (eIRA) codes which are efficiently encodable LDPC codes possessing very low error-rate floors and are appropriate for code rates 1/2 or greater. While efficiently encodable, the left-most (n-k)-by-k submatrix of an eIRA code parity-check matrix is random in nature, making efficient decoder implementation problematic. In the present paper, we present structured eIRA codes. We first present some ensemble results for the general class of eIRA codes, after which the subclass of structured eIRA (SeIRA) codes is defined. Software- and hardware-based performance results for SeIRA code designs (rates 0.5 to 0.9) are then presented.
eIRA codes are iteratively decodable low-density parity-check (LDPC) codes. They not only offer superior performance to alternative approaches, but they allow linear-time encoding. Well-designed eIRA codes also achieve extremely low error-rate floors. In this letter, we successfully implement a common FPGA platform for eIRA codes. As a demonstration, we took an example parity-check matrix from Example 4 in . For a maximum of seven iterations and 7 bits precision, the error-rate degradation is less than two tenths of a decibel compared to the double precision floating point result. It is important to note that there is no error rate floor close to BER of 10-12. Such a performance is often requested in practical applications, but has never been achieved by graphic codes in the literature so far as we know.
This paper is concerned with the construction of a class of nonbinary irregular repeat accumulate (IRA) codes. Since they are defined on the finite field GF(q) (q>2), we will refer to the constructed codes as q-ary IRA (QIRA) codes. While preserving the excellent error correcting capability of q-ary LDPC codes, QIRA codes can be efficiently encoded like conventional binary IRA codes. By adopting the progressive edge growth (PEG) algorithm to construct the parity check matrices, we can achieve the increased girth of their factor graphs and improved decoding performance. Simulation results show that, using the sum-product algorithm on GF(q), QIRA codes outperform binary LDPC codes and turbo codes in terms of bit error ratio and frame error ratio on AWGN channels. Especially, they could achieve excellent error performance when combined with high order modulations. Feasibility study indicates, with the use of the extended min-sum (EMS) decoding algorithm, QIRA codes are competitive candidates for practical applications.
Low-density parity-check (LDPC) codes have been intensively studied in the past decade for their capacity-approaching performance. LDPC code implementation complexity and the error-rate floor are still two significant unsolved issues which prevent their application in some important communication systems. In this dissertation, we make efforts toward solving these two problems by introducing the design of a class of LDPC codes called structured irregular repeat-accumulate (S-IRA) codes. These S-IRA codes combine several advantages of other types of LDPC codes, including low encoder and decoder complexities, flexibility in design, and good performance on different channels. It is also demonstrated in this dissertation that the S-IRA codes are suitable for rate-compatible code family design and a multi-rate code family has been designed which may be implemented with a single encoder/decoder.The study of the error floor problem of LDPC codes is very difficult because simulating LDPC codes on a computer at very low error rates takes an unacceptably long time. To circumvent this difficulty, we implemented a universal quasi-cyclic LDPC decoder on a field programmable gate array (FPGA) platform. This hardware platform accelerates the simulations by more than 100 times as compared to software simulations. We implemented two types of decoders with partially parallel architectures on the FPGA: a circulant-based decoder and a protograph-based decoder. By focusing on the protograph-based decoder, different soft iterative decoding algorithms were implemented. It provides us with a platform for quickly evaluating and analyzing different quasi-cyclic LDPC codes, including the S-IRA codes. A universal decoder architecture is also proposed which is capable of decoding of an arbitrary LDPC code, quasi-cyclic or not. Finally, we studied the low-floor problem by focusing on one example S-IRA code. We identified the weaknesses of the code and proposed several techniques to lower the error floor. We successfully demonstrated in hardware that it is possible to lower the floor substantially by encoder and decoder modifications, but the best solution appeared to be an outer BCH code.
Accumulate-repeat-accumulate-accumulate (ARAA) codes have been proposed, inspired by the recently proposed accumulate-repeat-accumulate (ARA) codes. These are error-correcting codes suitable for use in a variety of wireless data-communication systems that include noisy channels. ARAA codes can be regarded as serial turbolike codes or as a subclass of low-density parity-check (LDPC) codes, and, like ARA codes they have projected graph or protograph representations; these characteristics make it possible to design high-speed iterative decoders that utilize belief-propagation algorithms. The objective in proposing ARAA codes as a subclass of ARA codes was to enhance the error-floor performance of ARA codes while maintaining simple encoding structures and low maximum variable node degree.
Regular LDPC codes are a special class of low-density codes having an equal number of ones in each row and column of the parity check matrix describing the linear code. The uniform structure of regular LDPC codes allows a practical hardware implementation which can efficiently utilize the inherent parallelism of the message passing algorithm (MPA) commonly used to decode low-density codes. The class of {3,6} LDPC codes has been extensively studied and they have been proven to provide very good error performance, especially at lower SNR. {4,8} codes have not been analyzed nearly as much in the literature, mainly because their 'threshold,' the SNR where the waterfall region of the error performance curve begins, is typically a quarter of a dB or so worse than for comparable-length {3,6} codes. It has been proposed that {4,8} codes have better high SNR behavior, but until recently it was not possible to verify this conjecture. A new technique which can efficiently find error floors of LDPC codes now has the ability to illuminate just how good {4,8} codes are in the high SNR region-a result which is of great interest for many practical applications. This paper will analyze the error floor characteristics of some {4,8} codes and provide a simple algorithm for designing {4,8} codes with low error floors. A newly-designed rate-1/2 (1200,600) {4,8} code with a vastly superior error floor compared to codes of similar parameters is introduced