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Novel Parity-Preserving Designs of Reversible 4-Bit Comparator

Xuemei Qi, Fulong Chen, Hongtao Wang +2 more

International Journal of Theoretical PhysicsNov 18, 20137 citations

An Efficient Design of Reversible Multi-Bit Quantum Comparator Via Only a Single Ancillary Bit

Haiying Xia, Hai-Sheng Li, Han Zhang +2 more

International Journal of Theoretical PhysicsSep 14, 201829 citations

Design of 4-Bit Reversible Johnson Counter with Optimized Quantum Cost, Delay, and Number of Gate

Aman Agarwal, Heranmoy Maity, Arindam Biswas +2 more

Lecture notes in networks and systemsJan 1, 20193 citations

Design and Optimization of n-bit Reversible Binary Comparator

H. G. Rangaraju, Vinayak Hegde, K. Raja +1 more

Reversible logic has attracted significance attention in recent years, leading to different approaches such as synthesis, optimization, simulation and verification. In this paper, we propose the design and optimization of n-bit reversible binary comparator. The circuit for MSB and one-bit comparator cell using NOT, PG and CNOT gates are designed. The n-bit reversible binary comparator is designed using circuit for MSB as first stage to compare MSBs and one-bit comparator cell as second stage and so on to compare lesser significant bit positions. The power consumption, delay, garbage outputs and constant inputs are computed. It is observed that the quantum cost and garbage output values are less in the proposed technique compared to the existing approaches.Reversible logic has attracted significance attention in recent years, leading to different approaches such as synthesis, optimization, simulation and verification. In this paper, we propose the design and optimization of n-bit reversible binary comparator. The circuit for MSB and one-bit comparator cell using NOT, PG and CNOT gates are designed. The n-bit reversible binary comparator is designed using circuit for MSB as first stage to compare MSBs and one-bit comparator cell as second stage and so on to compare lesser significant bit positions. The power consumption, delay, garbage outputs and constant inputs are computed. It is observed that the quantum cost and garbage output values are less in the proposed technique compared to the existing approaches.

International Journal of Computer ApplicationsOct 20, 20125 citations

Design of fault tolerant n bit reversible comparator for optimization of garbage and Ancilla bits

H. V. Jayashree, V K Agarwal, P Venkatasree Charan +1 more

Reversible logic is the emerging topic for research due to its advantage of low energy consumption. Fault tolerant circuit design is required to give error free outputs. In this paper we present an optimized n bit Reversible Fault Tolerant Comparator design using parity preserving reversible logic gates. The Design involves MSB comparison as the first stage followed by Next Bit comparison stage which contributes for 1 bit garbage-less comparator design. The Design is generalized for n bit comparison. The performance parameters are analyzed for n bit. Our work outperforms the existing reversible fault tolerant comparator designs in terms of garbage output and Ancilla inputs or constant inputs. This efficiency of our design helps in reducing the footprint of the design.Reversible logic is the emerging topic for research due to its advantage of low energy consumption. Fault tolerant circuit design is required to give error free outputs. In this paper we present an optimized n bit Reversible Fault Tolerant Comparator design using parity preserving reversible logic gates. The Design involves MSB comparison as the first stage followed by Next Bit comparison stage which contributes for 1 bit garbage-less comparator design. The Design is generalized for n bit comparison. The performance parameters are analyzed for n bit. Our work outperforms the existing reversible fault tolerant comparator designs in terms of garbage output and Ancilla inputs or constant inputs. This efficiency of our design helps in reducing the footprint of the design.

International Conference on Circuits, Control, Communication and Computing (I4C)Nov 1, 20143 citations

Novel Design of Quantum/Reversible Ternary Comparator Circuits

Asma Taheri Monfared, Majid Haghparast

Journal of Computational and Theoretical NanoscienceDec 1, 201514 citations

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