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IEEE Vehicular Technology Conference

New implementation for the scalable LDPC-decoders

Yanping Li, Moon Ho Lee, Gi-Yean Hwang, Ju Yong Park

Published Feb 22, 2005• 1 citation
Publisher

Abstract

Trellis decoding of regular and irregular low-density parity-check (LDPC) codes and the corresponding decoder architectures are considered. Moreover, we propose a new approach for computing reliability metrics based on the BCJR algorithm that reduces the message switching activity in the decoder compared to existing approaches. The trellis decoding schedule is employed to decode LDPC codes using constituent soft-input soft-output (SISO) decoders that communicate through interleavers. The proposed tunable schedule exhibits a faster convergence behavior (up to 50% fewer iterations), and hence lower decoding latency, than the commonly employed two-phase schedule, and the corresponding decoder architecture has a significantly reduced memory requirement. Improvement in decoding gain (up to an order of magnitude for moderate-to-high SNR and small number of iterations) is achieved and structural regularity features in the form of permutation matrices further reduce interconnect complexity and improve decoding throughput.

DOI
10.1109/vetecs.2004.1387971

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Trellis decoding of regular and irregular low-density parity-check (LDPC) codes and the corresponding decoder architectures are considered. Moreover, we propose a new approach for computing reliability metrics based on the BCJR algorithm that reduces the message switching activity in the decoder compared to existing approaches. The trellis decoding schedule is employed to decode LDPC codes using constituent soft-input soft-output (SISO) decoders that communicate through interleavers. The proposed tunable schedule exhibits a faster convergence behavior (up to 50% fewer iterations), and hence lower decoding latency, than the commonly employed two-phase schedule, and the corresponding decoder architecture has a significantly reduced memory requirement. Improvement in decoding gain (up to an order of magnitude for moderate-to-high SNR and small number of iterations) is achieved and structural regularity features in the form of permutation matrices further reduce interconnect complexity and improve decoding throughput.
The implementation complexity of the decoder for low-density parity-check codes (LDPC) is dictated by memory and interconnect requirements. We propose new LDPC decoder architectures that reduce the need of message passing memory by 80% (for standard message passing)-55%(for layered decoding) and the router requirements by more than 50%. These novel architectures are based on scheduling of computation that results in "on the fly computation" of variable node and check node reliability messages. These architectures are targeted for quasi- cyclic LDPC codes such as array LDPC codes (regular QC-LDPC) and block LDPC codes (irregular QC-LDPC). FPGA and ASIC implementation results show substantial gains when compared to the existing work in the literature.
In this paper, we propose a turbo decoding message-passing (TDMP) algorithm to decode regular and irregular low-density parity-check (LDPC) codes. The TDMP algorithm has two main advantages over the commonly employed two-phase message-passing algorithm. First, it exhibits a faster convergence behavior (up to 50% less iterations), and improvement in coding gain (up to an order of magnitude for moderate-to-high SNR and small number of iterations). Second, the corresponding decoder architecture has a significantly reduced memory requirement that amounts to a savings of (75 + 25n//spl Sigma/ node-degrees)% > 75% for code-length n. A decoder architecture featuring the TDNW algorithm is also presented. Furthermore, we propose a new structure on the parity-check matrix of an LDPC code based on permutation matrices aimed at reducing interconnect complexity and improving decoding throughput. In addition, we construct a wide range of LDPC codes based on Ramanujan graphs which possess this structure.
Recent advances in coding theory have uncovered the previously forgotten power of Low-Density Parity-Check (LDPC) codes. Their popularity can be related to their relatively simple iterative decoders and their potential to achieve high performance close to shannon limit. These make them an attractive candidate for error correcting application in communication systems. In this thesis, we focus our research on the iterative decoding algorithms for Low-Density Parity-Check codes and present an improved decoding algorithm. First, the graph structure of LDPC codes is studied and a graph-based search algorithm to find the shortest closed walk and shortest cycle for each node of the graph is proposed. Then, the Deterministic schedule is applied on nodes of the graph with the objective of preserving the optimality of the algorithms. Finally, Hybrid Switch-Type technique is applied on the improved algorithms to provide a desirable complexity/performance trade-off. Hybrid Technique and Deterministic schedule are combined for decoding regular and irregular LDPC codes. The performance and complexity of the decoder is studied for Sum-Product and Gallager A algorithms. The result is a flexible decoder for any available LDPC code and any combination of decoding algorithms based on the communication systems need. In this technique, we benefit the high performance of soft-decision algorithms and low complexity of hard-decision algorithms by changing the decoding rule after a few iterations. Hence, a desirable performance can be obtained with less average number of soft iterations. Moreover, all the nodes do not update messages in each iteration. As a result, the total number of computations is reduced considerably
In the recent literature, turbo decoding message passing (TDMP) or layered decoding has been proposed for the decoding of low-density parity-check (LDPC) codes using a trellis-based BCJR algorithm in check node units (CNU). We present a new architecture for supporting rate compatible array LDPC codes that uses an offset-based min-sum decoding algorithm instead of the BCJR. The proposed architecture utilizes the value-reuse properties of min-sum and block-serial scheduling of computations, along with TDMP. This novel architecture has the following features: removal of memory needed to store the sum of the variable node messages and the channel values, removal of memory needed to store the variable node messages, 40%-72% savings in storage of extrinsic messages depending on rate of the codes, reduction of routers by 50%, and increase of throughput up to 2times. Implementations on our test-bed FPGA achieve decoded throughputs up to 1.36 Gbps and 2.27 Gbps for each iteration for (5,k) and (3,k) array LDPC codes, respectively. ASIC implementation achieve decoded throughputs up to 5.9 Gbps for each iteration for (5,k) array LDPC codes.
Non-binary low-density parity-check (NB-LDPC) codes have better error-correcting performance than their binary counterparts at the cost of higher decoding complexity when the code length is moderate. Compared to other NB-LDPC decoding algorithms, the iterative reliability-based majority-logic decoding can achieve better performance-complexity tradeoff. In this paper, an efficient partial-parallel shift-message decoder architecture is proposed for cyclic NB-LDPC codes based on the iterative soft reliability-based majority-logic decoding (ISRB-MLGD) algorithm. The message shifting is implemented by memories concatenated with variable node units to reduce the area. Although the accumulated soft reliabilities in the ISRB algorithm require longer word length, and accordingly longer critical path and larger memory, the decoder architecture and control logic can be simplified. Particularly, the check node units are modified so that the message switching network can be eliminated. Compared to the iterative hard reliability-based decoder for a (255, 175) NB-LDPC code over GF(28), the proposed ISRB decoder can achieve around 0.8dB coding gain with less than three times hardware complexity.
In this paper, we use a column-wise, row-wise approach for efficiently choosing reliable messages in decoding non-binary Low-Density Parity-Check (LDPC) codes, and build configurations with those reliable messages for updating check nodes. This method decreases the number of configurations compared to conventional trellis-based decoding algorithms. In addition, a novel algorithm with precomputed messages is proposed which improves decoding performance. Using the reduced configuration set with the improved message updating scheme it is shown that we can achieve an improved decoding performance while reducing the hardware complexity. Compared to trellis-based decoders, the proposed decoder reduces the number of required operations in computing check-to-variable messages and achieves better error-correcting performance.