The electromagnetic confinement of atomic ions has provided a useful testbed for many different applications in atomic physics, including laser cooling {1}, mass spectrometry {2}, and precision control of nearly-pure quantum states {3}. Recently, ion traps have been effectively applied to the growing field of quantum computation {4}, where the ability to isolate a single ion from its environment has made it an attractive architecture for a large-scale quantum information processor {5, 6, 7}. While many of the fundamental quantum computing building blocks have been demonstrated with trapped ions {8}, the technology for scaling to large numbers of ion quantum bits (qubits) is just beginning to develop. In this paper, we describe an important milestone on this path with the successful operation of an ion trap fabricated on an integrated gallium arsenide (GaAs) heterostructure, which could in principal scale to host a large array of ions.
We deploy a universal fault-tolerant quantum computing (FTQC) architecture based on error-detecting
[[8,3,2]] and
[[4,2,2]] codes on Quantinuum's Helios-1 trapped-ion quantum computer. We compile and execute ripple-carry adder (RCA) circuits for classical inputs up to five bits on this architecture. Uncomputing a workspace qubit provides an additional ``algorithmic check'' to detect errors. While available at both the physical and logical levels, this check synergizes with our architecture by increasing the effective fault distance of many circuit locations from two to four. Combining this algorithmic check with the error-detecting codes, we observed only a single logical failure in one-bit addition after burst-error filtering, yielding an estimated logical failure rate of
(6.0±5.9)×10−5. This is well below the
(3.5±1.3)×10−3 failure probability observed for one-bit addition on the same hardware in unencoded form. Two- and three-bit adders also showed performance improvements, while the longer four- and five-bit adders executed just above threshold.
Atomic-scale logic and the minimization of heating (dissipation) are both very high on the agenda for future computation hardware. An approach to achieve these would be to replace networks of transistors directly by classical reversible logic gates built from the coherent dynamics of a few interacting atoms. As superpositions are unnecessary before and after each such gate (inputs and outputs are bits), the dephasing time only needs to exceed a single gate operation time, while fault tolerance should be achieved with low overhead, by classical coding. Such gates could thus be a spin-off of quantum technology much before full-scale quantum computation. Thus motivated, we propose methods to realize the 3-bit Toffoli and Fredkin gates universal for classical reversible logic using a single time-independent 3-qubit Hamiltonian with realistic nearest neighbour two-body interactions. We also exemplify how these gates can be composed to make a larger circuit. We show that trapped ions may soon be scalable simulators for such architectures, and investigate the prospects with dopants in silicon.
We propose Shuttling-based Distributed Quantum Computing (SDQC), a hybrid architecture that combines the strengths of physical qubit shuttling and distributed quantum computing to enable scalable trapped-ion quantum computing. SDQC performs non-local quantum operations by distributing entangled ion qubits via deterministic shuttling, combining the high-fidelity and deterministic operations of shuttling-based architectures with the parallelism and pipelining advantages of distributed quantum computing. We present (1) a practical architecture incorporating quantum error correction (QEC), (2) pipelining strategies to exploit parallelism in entanglement distribution and measurement, and (3) a performance evaluation in terms of logical error rate and clock speed. For a 256-bit elliptic-curve discrete logarithm problem (ECDLP) instance, which requires 2,871 logical qubits at code distance 13, SDQC achieves a logical error rate which is
1.20−0.45+0.94×10−8 of Photonic DQC error rate and
3.79−2.84+5.09×10−3 of Quantum Charge-Coupled Device (QCCD) error rate, while providing 2.82 times faster logical clock speed than QCCD.