適用於IEEE 802.16e標準之中低密度同位檢查碼的快速收斂解碼方式與具有有效記憶體使用的超大型積體電路解碼器架構

鄭仲超

Published Jan 1, 2007• 0 citations

Abstract

In this thesis, we propose a modified iterative decoding algorithm to decode a special class of quasi-cyclic low-density parity-check (QC-LDPC) codes such as QC-LDPC codes used in the IEEE 802.16e standards. The proposed decoding is implemented by serially decoding block codes with identical parity-check matrix Hl derived from the parity-check matrix H of the QC-LDPC codes. The dimensions of Hl are much smaller than those of H. Extrinsic values can be passed between these block codes since the code bits of these block codes are overlapped. Hence, the proposed decoding can reduce the number of iterations required by up to forty percent without error performance degradation as compared to the conventional message passing algorithm. A partially-parallel very large-scale integration (VLSI) architecture is proposed to implement such a decoding algorithm. The proposed VLSI decoder can fully take advantage of the proposed decoding to increase its throughput. In addition, the proposed decoder only needs to store check-to-variable messages and hence is memory efficient.

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