Minimal-Latency Secure Function Evaluation

Donghang Lu, Albert Yu, Aniket Kate +1 more

While the practicality of secure multi-party computation (MPC) has been extensively analyzed and improved over the past decade, we are hitting the limits of efficiency with the traditional approaches of representing the computed functionalities as generic arithmetic or Boolean circuits. This work follows the design principle of identifying and constructing fast and provably-secure MPC protocols to evaluate useful high-level algebraic abstractions; thus, improving the efficiency of all applications relying on them. We present Polymath, a constant-round secure computation protocol suite for the secure evaluation of (multi-variate) polynomials of scalars and matrices, functionalities essential to numerous data-processing applications. Using precise natural precomputation and high-degree of parallelism prevalent in the modern computing environments, Polymath can make latency of secure polynomial evaluations of scalars and matrices independent of polynomial degree and matrix dimensions.

Özgür Dagdelen, Payman Mohassel, Daniele Venturi

Le, Xinyan, Zhu, Yao, Hu, Yulin +1 more

Physical layer security (PLS) is a potential solution for secure and reliable transmissions in future Ultra-Reliable and Low-Latency Communications (URLLC). This work jointly optimizes redundant bits and blocklength allocation in practical round-trip transmission scenarios. To minimize the leakage-failure probability, a metric that jointly characterizes security and reliability in PLS, we formulate an optimization problem for allocating both redundant bits and blocklength. By deriving the boundaries of the feasible set, we obtain the globally optimal solution for this integer optimization problem. To achieve more computationally efficient solutions, we propose a block coordinate descent (BCD) method that exploits the partial convexity of the objective function. Subsequently, we develop a majorization-minimization (MM) algorithm through convex approximation of the objective function, which further improves computational efficiency. Finally, we validate the performance of the three proposed approaches through simulations, demonstrating their practical applicability for future URLLC services.

Thomas H. Schneider

Özgür Dagdelen, Payman Mohassel, Daniele Venturi

Savo Glisic, Beatriz Lorenzo

Future IoT networks will demand increasingly lower latency for transmitting mission-critical information while simultaneously adopting quantum technologies to enhance security and accelerate information processing. This survey reviews the state-of-the-art in latency-optimal quantum circuit design, focusing on minimizing circuit latency without sacrificing essential functionality. The space is primarily allocated to the network level aspects, exploring balance between the network latency and the energy consumption, programmability and cost, while establishing a proper interface with the problems that should be delegated to the practical design carried on by circuit developers. Section I analyzes how aggressive latency reduction constrains the use ofuniversalandreversiblegates—both of which tend to increase circuit depth (latency). Universal gates enable programmability, while reversible gates reduce energy dissipation, yet both can extend circuit latency. Aware of these trade-offs, Section II discusses latency-optimal design methodologies and their implementation aspects. Next we discuss exact minimization of quantum circuits, presenting quantitative improvements. For instance, controlled-T gate implementations demonstrate reductions from 15 → 9 T gates (compression = 15/9), 16 → 12 CNOT gates (compression = 16/12), and 9 → 5 T-latency (compression = 9/5). Similarly, for a 1-bit full adder, reductions include 14 → 8 T gates (14/8), 12 → 10 CNOT gates (12/10), 4 → 2 H gates (2), and 8 → 2 T-latency (4).