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Asilomar Conference on Signals, Systems and Computers (ACSSC)

Finite precision implementation of LDPC coded M-ary modulation over wireless channels

Manyuan Shen, Huaning Niu, Hui Liu, James A. Ritcey

Published Jul 8, 2004• 4 citations
Publisher

Abstract

This paper studies the finite precision effects on the LDPC decoding performance with high order modulation over Rayleigh fading channels. We compare the performance of different quantization schemes and decoding algorithms using discretized density evolution over code ensembles of various code rates. We find that the min-sum algorithm with a simple correction term using 5 bits for quantization offers a very good performance in all code rate and modulation combinations. The loss is only 0.1 dB compared to floating point implementation. Direct implementation of the sum product algorithm with 6-bit quantization suffers a much larger performance loss when high rate LDPC codes are used. Both software simulations and test results of a hardware decoder implemented on FPGA verify these conclusions.

DOI
10.1109/acssc.2003.1291880

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This paper studies the finite precision effects on the LDPC decoding performance with high order modulation over Rayleigh fading channels. We compare the performance of different quantization schemes and decoding algorithms using discretized density evolution over code ensembles of various code rates. We find that the min-sum algorithm with a simple correction term using 5 bits for quantization offers a very good performance in all code rate and modulation combinations. The loss is only 0.1 dB compared to floating point implementation. Direct implementation of the sum product algorithm with 6-bit quantization suffers a much larger performance loss when high rate LDPC codes are used. Both software simulations and test results of a hardware decoder implemented on FPGA verify these conclusions.
LDPC codes have attracted much attention recently for their near-capacity performance and high throughput owing to parallel decoding architectures. While simulations are normally done with floating point computation, any practical implementation (ASIC or FPGA) will be built with fixed-point computation. Obviously, decoder speed will increase, and resource requirements will drop, with low-precision implementations, say 3,4, or 5-bit architectures. In this paper we study the effects of quantization in this regime, using density evolution and decoder simulation. Detailed sum-product decoder implementations are given, and performance losses relative to floating point decoding are given. In particular, 4-bit decoder architectures sustain only 0.1 dB penalty.
This paper analyzes the performance of quantized min-sum decoding algorithms for irregular low-density parity-check (LDPC) codes. For regular LDPC codes, it is known that the normalized or offset min-sum decoding algorithm with quantization bits less than 6 bits achieves good performances over wide range of signal-to-noise ratios (SNR). However, finite precision effects in decoding irregular LDPC codes are different from that in decoding regular LDPC codes which is caused by the difference of convergence speeds between low degree nodes and high degree nodes. This paper proposes a novel method to improve the performance of the conventional normalized or offset min-sum decoding algorithm when it is approximated with finite precision for hardware implementations. The proposed method applies down-scaling factors to intrinsic information which has effects on increasing the reliability of extrinsic information at variable nodes and compensating the quantization errors caused by finite precision. Computer simulation results for irregular LDPC codes show that the proposed normalized and offset min-sum decoding algorithms achieve better performances at high SNR compared to the conventional normalized and offset min-sum algorithms under (6:2) quantization scheme.
Low-Density Parity-Check(LDPC) codes are typical of preeminent performance approaching Shannon’s capacity limit.This paper studies the LDPC codes min-sum decoding algorithm,and a min-sum algorithm in QPSK modulation based on integer operation is proposed for decoding LDPC codes.All the variables are fixed length integers in this algorithm,so it is very convenient for hardware implementation.Simulation results show that its performance is close to that of sum-product algorithm whose variables are high precision floating point numbers.
It's common to use high-precision floating-point operations on theoretical study of the Low Density Parity Check (LDPC) codes, but it is difficult to implement it in practical application. Therefore, there is a great need to design effective quantitative method which enables us to implement it in hardware easily. In this paper, the min-sum decoding algorithm of LDPC codes for 8PSK modulation is studied in detail, and the method of the uniform quantization is analyzed and deduced. With this method to quantify the initial message, the variable messages and check messages are converted into integers after each iteration. Then the min-sum decoding algorithm based on integer arithmetic for 8PSK modulation is implemented. Simulation results demonstrate that the performance of the min-sum decoding algorithm with the uniform quantization is close to that of the high-precision floating-point sum-product decoding algorithm. Meanwhile, all the variables in the algorithm are fixed-length integers, so it is convenient for hardware implementation.
Low-density parity-check (LDPC) codes are among the most powerful known error correcting codes and they have been shown to achieve performance very close to the Shannon bound. In practical hardware implementations of LDPC decoders, bit error rate performances are affected strongly by fixed-point representation of processed data and, although many papers have been published in recent years on the subject of LDPC codes, only a few of them report results on the effects of finite precision. In the paper two novel arithmetic approximations for the basic processing operations of the decoding algorithm are presented. The two proposed solutions are analysed in terms of bit error rate performance for different finite precison representations of both external and internal data; the estimated performance loss is comparable to that reported by previous works and limited to approximately 0.1 dB for cases of interests. However the proposed solutions support a reduced complexity formulation of the decoding algorithm, so enabling the implementation of flexible decoders that can be adapted to different LDPC codes, block sizes and code rates.
In this paper, we analyze the performance of quantized offset min-sum (MS) decoding algorithm and propose an optimally quantized offset MS algorithm for a flexible low-density parity-check (LDPC) decoder. It is known that the offset MS decoding algorithm is implemented with simplified hardware complexity and achieves good decoding performance. However, the finite precision effects in decoding LDPC codes result in performance different from floating point. The performance degradation is caused by different dynamic ranges of input data at high signal-to-noise ratio (SNR). The proposed offset MS algorithm uses the received data directly instead of log-likelihood ratio (LLR) data as the intrinsic information. It can achieve better performance than the conventional one since its offset factor is more effective at a wide range of SNR and the intrinsic information is quantized more robustly since it is independent of channel information. Also, it is possible for the proposed scheme to use a same quantization scheme for a flexible LDPC decoder, which can decode several kinds of LDPC codes. Simulation results show that our optimally quantized offset MS algorithms with 5-bits for (1728, 864) and (1728, 1296) irregular LDPC codes achieve better performance compared with the conventional offset MS algorithms with 6-bits quantization scheme.