Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEICE Transactions on Electronics

Design considerations of data-driven self-timed rsfq adder circuits

Nobuyuki Yoshikawa, Hiroshi Tago, Kaoru Yoneyama

Published Oct 25, 1998• 3 citations
OpenAlex

Related papers

Design and testing of data-driven self-timed RSFQ shift register

Z.J. Deng, Nobuyuki Yoshikawa, Stephen R. Whiteley +1 more

Applied Superconductivity•Oct 1, 1999•1 citation

Data-driven self-timed RSFQ demultiplexer

Nobuyuki Yoshikawa, Z.J. Deng, Stephen R. Whiteley +1 more

Applied Superconductivity•Jul 1, 1998•5 citations

Optimised Asynchronous Self-Timing for Superconducting RSFQ Logic Circuits

Ieee Africon

•Jan 1, 2004•0 citations

Data-driven self-timed RSFQ digital integrated circuit and system

Z.J. Deng, Nobuyuki Yoshikawa, Stephen R. Whiteley +1 more

A novel asynchronous timing scheme, data-driven self-timing (DDST) is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ) superconductive integrated circuits. In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to drive the RSFQ circuit and system. The essence of the self-timing scheme is to localize the system timing in order to avoid the overhead of global clock distribution, and to minimize the timing uncertainty. The DDST scheme has been applied to the design of a shift register, a demultiplexor, and a self-timed high speed digital test system. In this paper, test results of a 4-bit DDST shift register and a high speed on-chip clock generator will be presented to demonstrate the successful DDST operation of RSFQ integrated circuits at a rate of 20 Gb/s.

IEEE Transactions on Applied Superconductivity•Jun 1, 1997•104 citations

Design aspects of complex asynchronous RSFQ digital circuits

Boyko Dimov, Valeri Mladenov, Valery Todorov +2 more

CD-ROM-Ausg.:#R#<br/>Information technology and electrical engineering - devices and systems, materials and technologies for the future : 51. IWK, Internationales Wissenschaftliches Kolloquium ; proceedings ; 11 - 15 September 2006 / Faculty of Electrical and Information Technology, Technische Universität Ilmenau. - Ilmenau : Verl. ISLE, 2006. - ISBN 3-938843-16-0•Jun 24, 2009•1 citation

Simulation and 18 Gb/s testing of a data-driven self-timed RSFQ demultiplexer

Nobuyuki Yoshikawa, Z.J. Deng, Stephen R. Whiteley +1 more

We have developed a data-driven self-timed (DDST) rapid-single-flux-quantum (RSFQ) demultiplexer (demux) for the interface between on-chip high-speed RSFQ circuits and off-chip low-speed circuits. In order to eliminate the timing issue in a synchronous clocking system we employed the DDST architecture, where a clock signal is localized within a 2-bit basic demux module and dual rail lines are used to transfer the timing information between the modules. A larger demux can be produced simply by connecting the 2-bit modules in a tree structure. The DDST demux was designed for 10 Gb/s operation with sufficient dc bias margin using HYPRES 1 kA/cm/sup 2/ Nb process. We have successfully tested operation of the 2-bit demux up to 18 GHz using the DDST on-chip high-speed test system which was developed in our group.

IEEE Transactions on Applied Superconductivity•Jun 1, 1999•9 citations
A novel asynchronous timing scheme, data-driven self-timing (DDST) is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ) superconductive integrated circuits. In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to drive the RSFQ circuit and system. The essence of the self-timing scheme is to localize the system timing in order to avoid the overhead of global clock distribution, and to minimize the timing uncertainty. The DDST scheme has been applied to the design of a shift register, a demultiplexor, and a self-timed high speed digital test system. In this paper, test results of a 4-bit DDST shift register and a high speed on-chip clock generator will be presented to demonstrate the successful DDST operation of RSFQ integrated circuits at a rate of 20 Gb/s.
We have developed a data-driven self-timed (DDST) rapid-single-flux-quantum (RSFQ) demultiplexer (demux) for the interface between on-chip high-speed RSFQ circuits and off-chip low-speed circuits. In order to eliminate the timing issue in a synchronous clocking system we employed the DDST architecture, where a clock signal is localized within a 2-bit basic demux module and dual rail lines are used to transfer the timing information between the modules. A larger demux can be produced simply by connecting the 2-bit modules in a tree structure. The DDST demux was designed for 10 Gb/s operation with sufficient dc bias margin using HYPRES 1 kA/cm/sup 2/ Nb process. We have successfully tested operation of the 2-bit demux up to 18 GHz using the DDST on-chip high-speed test system which was developed in our group.