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European Conference on Circuit Theory and Design

A scheme to enhance the error-correcting capability of encoded quantum information

Han-Wei Wang, I.-M. Tsai, Chih-Neng Chung, Sy‐Yen Kuo

Published Oct 11, 2006• 2 citations
Publisher

Abstract

In a noisy quantum channel, burst errors usually causes multiple bit-phase flips that are adjacent to each other (Vatan, Raichowdry and Anantram, 1999; Grassl and Beth, 2000). This effectively makes some quantum error-correcting codes to be unusable. In this paper, the concept of interleaving qubit transmission is proposed. By using the interleaving method in a quantum information transmission process, burst errors in a quantum channel are re-arranged into different time slots. This relocation makes the error bits non-adjacent and hence increases the probability of information recovery. Note that although this scheme enhances the error-correcting capability of the encoded quantum information, it does not increase the redundancy of the code, because only the qubit sequences are relocated. In addition to the interleaving scheme, implementation of the proposed scheme at the circuit level is also discussed in this paper.

DOI
10.1109/ecctd.2005.1523039

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In a noisy quantum channel, burst errors usually causes multiple bit-phase flips that are adjacent to each other (Vatan, Raichowdry and Anantram, 1999; Grassl and Beth, 2000). This effectively makes some quantum error-correcting codes to be unusable. In this paper, the concept of interleaving qubit transmission is proposed. By using the interleaving method in a quantum information transmission process, burst errors in a quantum channel are re-arranged into different time slots. This relocation makes the error bits non-adjacent and hence increases the probability of information recovery. Note that although this scheme enhances the error-correcting capability of the encoded quantum information, it does not increase the redundancy of the code, because only the qubit sequences are relocated. In addition to the interleaving scheme, implementation of the proposed scheme at the circuit level is also discussed in this paper.
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